m68knommu: merge ColdFire 5249 and 525x definitions
The ColdFire 5249 and 525x family of SoCs are very similar. Most of the internals are the same, and are mapped the same. We can use a single set of peripheral definitions for all of them. So merge the current m5249sim.h and m525xsim.h definitions into a single file. The 5249 is now obsolete, and the 525x parts are current, so I have chosen to move everything into the existing m525xsim.h file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer
parent
9da1a84a91
commit
5a4acf3eac
@ -1,269 +0,0 @@
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/****************************************************************************/
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/*
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* m5249sim.h -- ColdFire 5249 System Integration Module support.
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*
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* (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
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*/
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/****************************************************************************/
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#ifndef m5249sim_h
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#define m5249sim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m5249)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 2)
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#include <asm/m52xxacr.h>
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/*
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* The 5249 has a second MBAR region, define its address.
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*/
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#define MCF_MBAR2 0x80000000
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/*
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* Define the 5249 SIM register set addresses.
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*/
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#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
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#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
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#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
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#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
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#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
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#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
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#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
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#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
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#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
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#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
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#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
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#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
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#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
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#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
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#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
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#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
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#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
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#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
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#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
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#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
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#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
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#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
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#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
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#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
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#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
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#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
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#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
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#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
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#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
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#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
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#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
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#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
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#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
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#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
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#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
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#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
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#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
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#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
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/*
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* Timer module.
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*/
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#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
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#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
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#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
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/*
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* QSPI module.
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*/
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#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
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#define MCFQSPI_SIZE 0x40 /* Register set size */
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#define MCFQSPI_CS0 29
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#define MCFQSPI_CS1 24
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#define MCFQSPI_CS2 21
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#define MCFQSPI_CS3 22
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/*
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* DMA unit base addresses.
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*/
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#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
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#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
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#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
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#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
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/*
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* Some symbol defines for the above...
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*/
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#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
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#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
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#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
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#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
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#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
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#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
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#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
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#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
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#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
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#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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#define MCF_IRQ_UART0 73 /* UART0 */
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#define MCF_IRQ_UART1 74 /* UART1 */
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/*
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* General purpose IO registers (in MBAR2).
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*/
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#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
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#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
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#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
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#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
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#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
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#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
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#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
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#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
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#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
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#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
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#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
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#define MCFSIM2_INTLEVEL1 (MCF_MBAR2 + 0x140) /* Intr level reg 1 */
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#define MCFSIM2_INTLEVEL2 (MCF_MBAR2 + 0x144) /* Intr level reg 2 */
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#define MCFSIM2_INTLEVEL3 (MCF_MBAR2 + 0x148) /* Intr level reg 3 */
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#define MCFSIM2_INTLEVEL4 (MCF_MBAR2 + 0x14c) /* Intr level reg 4 */
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#define MCFSIM2_INTLEVEL5 (MCF_MBAR2 + 0x150) /* Intr level reg 5 */
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#define MCFSIM2_INTLEVEL6 (MCF_MBAR2 + 0x154) /* Intr level reg 6 */
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#define MCFSIM2_INTLEVEL7 (MCF_MBAR2 + 0x158) /* Intr level reg 7 */
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#define MCFSIM2_INTLEVEL8 (MCF_MBAR2 + 0x15c) /* Intr level reg 8 */
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#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
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#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
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#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
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/*
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* Define the base interrupt for the second interrupt controller.
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* We set it to 128, out of the way of the base interrupts, and plenty
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* of room for its 64 interrupts.
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*/
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#define MCFINTC2_VECBASE 128
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#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32)
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#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33)
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#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34)
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#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35)
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#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36)
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#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37)
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#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38)
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#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39)
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 64
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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/****************************************************************************/
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#ifdef __ASSEMBLER__
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/*
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* The M5249C3 board needs a little help getting all its SIM devices
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* initialized at kernel start time. dBUG doesn't set much up, so
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* we need to do it manually.
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*/
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.macro m5249c3_setup
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/*
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* Set MBAR1 and MBAR2, just incase they are not set.
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*/
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movel #0x10000001,%a0
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movec %a0,%MBAR /* map MBAR region */
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subql #1,%a0 /* get MBAR address in a0 */
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movel #0x80000001,%a1
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movec %a1,#3086 /* map MBAR2 region */
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subql #1,%a1 /* get MBAR2 address in a1 */
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/*
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* Move secondary interrupts to their base (128).
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*/
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moveb #MCFINTC2_VECBASE,%d0
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moveb %d0,0x16b(%a1) /* interrupt base register */
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/*
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* Work around broken CSMR0/DRAM vector problem.
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*/
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movel #0x001F0021,%d0 /* disable C/I bit */
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movel %d0,0x84(%a0) /* set CSMR0 */
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/*
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* Disable the PLL firstly. (Who knows what state it is
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* in here!).
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*/
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movel 0x180(%a1),%d0 /* get current PLL value */
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andl #0xfffffffe,%d0 /* PLL bypass first */
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movel %d0,0x180(%a1) /* set PLL register */
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nop
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#if CONFIG_CLOCK_FREQ == 140000000
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/*
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* Set initial clock frequency. This assumes M5249C3 board
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* is fitted with 11.2896MHz crystal. It will program the
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* PLL for 140MHz. Lets go fast :-)
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*/
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movel #0x125a40f0,%d0 /* set for 140MHz */
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movel %d0,0x180(%a1) /* set PLL register */
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orl #0x1,%d0
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movel %d0,0x180(%a1) /* set PLL register */
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#endif
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/*
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* Setup CS1 for ethernet controller.
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* (Setup as per M5249C3 doco).
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*/
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movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
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movel %d0,0x8c(%a0)
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movel #0x001f0021,%d0 /* CS1 size of 1Mb */
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movel %d0,0x90(%a0)
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movew #0x0080,%d0 /* CS1 = 16bit port, AA */
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movew %d0,0x96(%a0)
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/*
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* Setup CS2 for IDE interface.
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*/
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movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
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movel %d0,0x98(%a0)
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movel #0x001f0001,%d0 /* CS2 size of 1MB */
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movel %d0,0x9c(%a0)
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movew #0x0080,%d0 /* CS2 = 16bit, TA */
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movew %d0,0xa2(%a0)
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movel #0x00107000,%d0 /* IDEconfig1 */
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movel %d0,0x18c(%a1)
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movel #0x000c0400,%d0 /* IDEconfig2 */
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movel %d0,0x190(%a1)
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movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
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orl %d0,0xc(%a1) /* function GPIO19 */
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orl %d0,0x8(%a1) /* enable GPIO19 as output */
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orl %d0,0x4(%a1) /* de-assert IDE reset */
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.endm
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#define PLATFORM_SETUP m5249c3_setup
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#endif /* __ASSEMBLER__ */
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/****************************************************************************/
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#endif /* m5249sim_h */
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@ -12,6 +12,11 @@
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#define m525xsim_h
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/****************************************************************************/
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/*
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* This header supports ColdFire 5249, 5251 and 5253. There are a few
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* little differences between them, but most of the peripheral support
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* can be used by all of them.
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*/
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#define CPU_NAME "COLDFIRE(m525x)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 2)
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@ -65,6 +70,8 @@
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#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
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#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
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#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
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#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
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#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
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/*
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* Secondary Interrupt Controller (in MBAR2)
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@ -101,11 +108,17 @@
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#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
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#define MCFQSPI_SIZE 0x40 /* Register set size */
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#ifdef CONFIG_M5249
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#define MCFQSPI_CS0 29
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#define MCFQSPI_CS1 24
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#define MCFQSPI_CS2 21
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#define MCFQSPI_CS3 22
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#else
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#define MCFQSPI_CS0 15
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#define MCFQSPI_CS1 16
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#define MCFQSPI_CS2 24
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#define MCFQSPI_CS3 28
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#endif
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/*
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* I2C module.
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@ -115,6 +128,7 @@
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#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
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#define MCFI2C_SIZE1 0x20 /* Register set size */
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/*
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* DMA unit base addresses.
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*/
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@ -163,6 +177,7 @@
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#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
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#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
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#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
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#define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39)
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#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
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#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
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@ -183,12 +198,111 @@
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#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
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#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
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#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
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#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
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#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 64
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#ifdef CONFIG_M5249
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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#else
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#define MCFGPIO_IRQ_MAX 7
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#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
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#endif
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/****************************************************************************/
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#ifdef __ASSEMBLER__
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#ifdef CONFIG_M5249C3
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/*
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* The M5249C3 board needs a little help getting all its SIM devices
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* initialized at kernel start time. dBUG doesn't set much up, so
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* we need to do it manually.
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*/
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.macro m5249c3_setup
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/*
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* Set MBAR1 and MBAR2, just incase they are not set.
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*/
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movel #0x10000001,%a0
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movec %a0,%MBAR /* map MBAR region */
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subql #1,%a0 /* get MBAR address in a0 */
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movel #0x80000001,%a1
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movec %a1,#3086 /* map MBAR2 region */
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subql #1,%a1 /* get MBAR2 address in a1 */
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/*
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* Move secondary interrupts to their base (128).
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*/
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moveb #MCFINTC2_VECBASE,%d0
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moveb %d0,0x16b(%a1) /* interrupt base register */
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/*
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* Work around broken CSMR0/DRAM vector problem.
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*/
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movel #0x001F0021,%d0 /* disable C/I bit */
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movel %d0,0x84(%a0) /* set CSMR0 */
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/*
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* Disable the PLL firstly. (Who knows what state it is
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* in here!).
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*/
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movel 0x180(%a1),%d0 /* get current PLL value */
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andl #0xfffffffe,%d0 /* PLL bypass first */
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movel %d0,0x180(%a1) /* set PLL register */
|
||||
nop
|
||||
|
||||
#if CONFIG_CLOCK_FREQ == 140000000
|
||||
/*
|
||||
* Set initial clock frequency. This assumes M5249C3 board
|
||||
* is fitted with 11.2896MHz crystal. It will program the
|
||||
* PLL for 140MHz. Lets go fast :-)
|
||||
*/
|
||||
movel #0x125a40f0,%d0 /* set for 140MHz */
|
||||
movel %d0,0x180(%a1) /* set PLL register */
|
||||
orl #0x1,%d0
|
||||
movel %d0,0x180(%a1) /* set PLL register */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Setup CS1 for ethernet controller.
|
||||
* (Setup as per M5249C3 doco).
|
||||
*/
|
||||
movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
|
||||
movel %d0,0x8c(%a0)
|
||||
movel #0x001f0021,%d0 /* CS1 size of 1Mb */
|
||||
movel %d0,0x90(%a0)
|
||||
movew #0x0080,%d0 /* CS1 = 16bit port, AA */
|
||||
movew %d0,0x96(%a0)
|
||||
|
||||
/*
|
||||
* Setup CS2 for IDE interface.
|
||||
*/
|
||||
movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
|
||||
movel %d0,0x98(%a0)
|
||||
movel #0x001f0001,%d0 /* CS2 size of 1MB */
|
||||
movel %d0,0x9c(%a0)
|
||||
movew #0x0080,%d0 /* CS2 = 16bit, TA */
|
||||
movew %d0,0xa2(%a0)
|
||||
|
||||
movel #0x00107000,%d0 /* IDEconfig1 */
|
||||
movel %d0,0x18c(%a1)
|
||||
movel #0x000c0400,%d0 /* IDEconfig2 */
|
||||
movel %d0,0x190(%a1)
|
||||
|
||||
movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
|
||||
orl %d0,0xc(%a1) /* function GPIO19 */
|
||||
orl %d0,0x8(%a1) /* enable GPIO19 as output */
|
||||
orl %d0,0x4(%a1) /* de-assert IDE reset */
|
||||
.endm
|
||||
|
||||
#define PLATFORM_SETUP m5249c3_setup
|
||||
|
||||
#endif /* CONFIG_M5249C3 */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
/****************************************************************************/
|
||||
#endif /* m525xsim_h */
|
||||
|
||||
@ -24,10 +24,7 @@
|
||||
#elif defined(CONFIG_M523x)
|
||||
#include <asm/m523xsim.h>
|
||||
#include <asm/mcfintc.h>
|
||||
#elif defined(CONFIG_M5249)
|
||||
#include <asm/m5249sim.h>
|
||||
#include <asm/mcfintc.h>
|
||||
#elif defined(CONFIG_M525x)
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
|
||||
#include <asm/m525xsim.h>
|
||||
#include <asm/mcfintc.h>
|
||||
#elif defined(CONFIG_M527x)
|
||||
|
||||
@ -21,7 +21,7 @@ static void intc2_irq_gpio_mask(struct irq_data *d)
|
||||
{
|
||||
u32 imr;
|
||||
imr = readl(MCFSIM2_GPIOINTENABLE);
|
||||
imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
|
||||
imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0));
|
||||
writel(imr, MCFSIM2_GPIOINTENABLE);
|
||||
}
|
||||
|
||||
@ -29,13 +29,13 @@ static void intc2_irq_gpio_unmask(struct irq_data *d)
|
||||
{
|
||||
u32 imr;
|
||||
imr = readl(MCFSIM2_GPIOINTENABLE);
|
||||
imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
|
||||
imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0));
|
||||
writel(imr, MCFSIM2_GPIOINTENABLE);
|
||||
}
|
||||
|
||||
static void intc2_irq_gpio_ack(struct irq_data *d)
|
||||
{
|
||||
writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
|
||||
writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
|
||||
}
|
||||
|
||||
static struct irq_chip intc2_irq_gpio_chip = {
|
||||
@ -50,7 +50,7 @@ static int __init mcf_intc2_init(void)
|
||||
int irq;
|
||||
|
||||
/* GPIO interrupt sources */
|
||||
for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
|
||||
for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) {
|
||||
irq_set_chip(irq, &intc2_irq_gpio_chip);
|
||||
irq_set_handler(irq, handle_edge_irq);
|
||||
}
|
||||
|
||||
@ -28,8 +28,8 @@ static struct resource m5249_smc91x_resources[] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = MCFINTC2_GPIOIRQ6,
|
||||
.end = MCFINTC2_GPIOIRQ6,
|
||||
.start = MCF_IRQ_GPIO6,
|
||||
.end = MCF_IRQ_GPIO6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
@ -75,8 +75,8 @@ static void __init m5249_smc91x_init(void)
|
||||
gpio = readl(MCFSIM2_GPIOINTENABLE);
|
||||
writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
|
||||
|
||||
gpio = readl(MCFSIM2_INTLEVEL5);
|
||||
writel(gpio | 0x04000000, MCFSIM2_INTLEVEL5);
|
||||
gpio = readl(MCFINTC2_INTPRI5);
|
||||
writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_M5249C3 */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user