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Merge branch 'master' into mm-hotfixes-stable

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Andrew Morton 2024-01-17 12:59:32 -08:00
commit 5aa1c96e8e
220 changed files with 2547 additions and 1571 deletions
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2
Documentation/admin-guide/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features
.. kernel-feat:: features

5
Documentation/admin-guide/hw_random.rst
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@ -14,10 +14,9 @@ into that core.
To make the most effective use of these mechanisms, you
should download the support software as well. Download the
latest version of the "rng-tools" package from the
hw_random driver's official Web site:
latest version of the "rng-tools" package from:
http://sourceforge.net/projects/gkernel/
https://github.com/nhorman/rng-tools
Those tools use /dev/hwrng to fill the kernel entropy pool,
which is used internally and exported by the /dev/urandom and

2
Documentation/arch/arc/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features arc
.. kernel-feat:: features arc

2
Documentation/arch/arm/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features arm
.. kernel-feat:: features arm

2
Documentation/arch/arm64/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features arm64
.. kernel-feat:: features arm64

2
Documentation/arch/loongarch/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features loongarch
.. kernel-feat:: features loongarch

2
Documentation/arch/m68k/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features m68k
.. kernel-feat:: features m68k

2
Documentation/arch/mips/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features mips
.. kernel-feat:: features mips

2
Documentation/arch/nios2/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features nios2
.. kernel-feat:: features nios2

2
Documentation/arch/openrisc/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features openrisc
.. kernel-feat:: features openrisc

2
Documentation/arch/parisc/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features parisc
.. kernel-feat:: features parisc

2
Documentation/arch/powerpc/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features powerpc
.. kernel-feat:: features powerpc

2
Documentation/arch/riscv/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features riscv
.. kernel-feat:: features riscv

122
Documentation/arch/riscv/hwprobe.rst
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@ -12,7 +12,7 @@ is defined in <asm/hwprobe.h>::
};
long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
size_t cpu_count, cpu_set_t *cpus,
size_t cpusetsize, cpu_set_t *cpus,
unsigned int flags);
The arguments are split into three groups: an array of key-value pairs, a CPU
@ -20,12 +20,26 @@ set, and some flags. The key-value pairs are supplied with a count. Userspace
must prepopulate the key field for each element, and the kernel will fill in the
value if the key is recognized. If a key is unknown to the kernel, its key field
will be cleared to -1, and its value set to 0. The CPU set is defined by
CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will
be only be valid if all CPUs in the given set have the same value. Otherwise -1
will be returned. For boolean-like keys, the value returned will be a logical
AND of the values for the specified CPUs. Usermode can supply NULL for cpus and
0 for cpu_count as a shortcut for all online CPUs. There are currently no flags,
this value must be zero for future compatibility.
CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
arch, impl), the returned value will only be valid if all CPUs in the given set
have the same value. Otherwise -1 will be returned. For boolean-like keys, the
value returned will be a logical AND of the values for the specified CPUs.
Usermode can supply NULL for ``cpus`` and 0 for ``cpusetsize`` as a shortcut for
all online CPUs. The currently supported flags are:
* :c:macro:`RISCV_HWPROBE_WHICH_CPUS`: This flag basically reverses the behavior
of sys_riscv_hwprobe(). Instead of populating the values of keys for a given
set of CPUs, the values of each key are given and the set of CPUs is reduced
by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
How matching is done depends on the key type. For value-like keys, matching
means to be the exact same as the value. For boolean-like keys, matching
means the result of a logical AND of the pair's value with the CPU's value is
exactly the same as the pair's value. Additionally, when ``cpus`` is an empty
set, then it is initialized to all online CPUs which fit within it, i.e. the
CPU set returned is the reduction of all the online CPUs which can be
represented with a CPU set of size ``cpusetsize``.
All other flags are reserved for future compatibility and must be zero.
On success 0 is returned, on failure a negative error code is returned.
@ -80,6 +94,100 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
* :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
in version 1.0 of the Bit-Manipulation ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as
defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as
defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as
defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as
defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as
defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as
defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as
defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as
defined in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
in version 1.0 of the Scalar Crypto ISA extensions.
* :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
* :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
as defined in the RISC-V ISA manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
supported as defined in the RISC-V ISA manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
is supported as defined in the RISC-V ISA manual.
* :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
("Remove draft warnings from Zvfh[min]").
* :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
("Remove draft warnings from Zvfh[min]").
* :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as
defined in the RISC-V ISA manual starting from commit 056b6ff467c7
("Zfa is ratified").
* :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as
defined in the RISC-V ISA manual starting from commit 5618fb5a216b
("Ztso is now ratified.")
* :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as
defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
from commit 5059e0ca641c ("update to ratified").
* :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
defined in the RISC-V Integer Conditional (Zicond) operations extension
manual starting from commit 95cf1f9 ("Add changes requested by Ved
during signoff")
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.

2
Documentation/arch/s390/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features s390
.. kernel-feat:: features s390

2
Documentation/arch/sh/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features sh
.. kernel-feat:: features sh

2
Documentation/arch/sparc/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features sparc
.. kernel-feat:: features sparc

2
Documentation/arch/x86/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features x86
.. kernel-feat:: features x86

2
Documentation/arch/xtensa/features.rst
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@ -1,3 +1,3 @@
.. SPDX-License-Identifier: GPL-2.0
.. kernel-feat:: $srctree/Documentation/features xtensa
.. kernel-feat:: features xtensa

2
Documentation/core-api/workqueue.rst
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@ -446,7 +446,7 @@ The command used: ::
There are 24 issuers, each issuing 64 IOs concurrently. ``--verify=sha512``
makes ``fio`` generate and read back the content each time which makes
execution locality matter between the issuer and ``kcryptd``. The followings
execution locality matter between the issuer and ``kcryptd``. The following
are the read bandwidths and CPU utilizations depending on different affinity
scope settings on ``kcryptd`` measured over five runs. Bandwidths are in
MiBps, and CPU util in percents.

11
Documentation/dev-tools/kunit/running_tips.rst
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@ -139,6 +139,17 @@ If your installed version of gcc doesn't work, you can tweak the steps:
$ ./tools/testing/kunit/kunit.py run --make_options=CC=/usr/bin/gcc-6
$ lcov -t "my_kunit_tests" -o coverage.info -c -d .kunit/ --gcov-tool=/usr/bin/gcov-6
Alternatively, LLVM-based toolchains can also be used:
.. code-block:: bash
# Build with LLVM and append coverage options to the current config
$ ./tools/testing/kunit/kunit.py run --make_options LLVM=1 --kunitconfig=.kunit/ --kunitconfig=tools/testing/kunit/configs/coverage_uml.config
$ llvm-profdata merge -sparse default.profraw -o default.profdata
$ llvm-cov export --format=lcov .kunit/vmlinux -instr-profile default.profdata > coverage.info
# The coverage.info file is in lcov-compatible format and it can be used to e.g. generate HTML report
$ genhtml -o /tmp/coverage_html coverage.info
Running tests manually
======================

1
Documentation/devicetree/bindings/riscv/cpus.yaml
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@ -32,6 +32,7 @@ properties:
oneOf:
- items:
- enum:
- amd,mbv32
- andestech,ax45mp
- canaan,k210
- sifive,bullet0

219
Documentation/devicetree/bindings/riscv/extensions.yaml
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@ -171,6 +171,12 @@ properties:
memory types as ratified in the 20191213 version of the privileged
ISA specification.
- const: zacas
description: |
The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
is supported as ratified at commit 5059e0ca641c ("update to
ratified") of the riscv-zacas.
- const: zba
description: |
The standard Zba bit-manipulation extension for address generation
@ -190,12 +196,111 @@ properties:
multiplication as ratified at commit 6d33919 ("Merge pull request
#158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
- const: zbkb
description:
The standard Zbkb bitmanip instructions for cryptography as ratified
in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zbkc
description:
The standard Zbkc carry-less multiply instructions as ratified
in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zbkx
description:
The standard Zbkx crossbar permutation instructions as ratified
in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zbs
description: |
The standard Zbs bit-manipulation extension for single-bit
instructions as ratified at commit 6d33919 ("Merge pull request #158
from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
- const: zfa
description:
The standard Zfa extension for additional floating point
instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
riscv-isa-manual.
- const: zfh
description:
The standard Zfh extension for 16-bit half-precision binary
floating-point instructions, as ratified in commit 64074bc ("Update
version numbers for Zfh/Zfinx") of riscv-isa-manual.
- const: zfhmin
description:
The standard Zfhmin extension which provides minimal support for
16-bit half-precision binary floating-point instructions, as ratified
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
riscv-isa-manual.
- const: zk
description:
The standard Zk Standard Scalar cryptography extension as ratified
in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zkn
description:
The standard Zkn NIST algorithm suite extensions as ratified in
version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zknd
description: |
The standard Zknd for NIST suite: AES decryption instructions as
ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zkne
description: |
The standard Zkne for NIST suite: AES encryption instructions as
ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zknh
description: |
The standard Zknh for NIST suite: hash function instructions as
ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zkr
description:
The standard Zkr entropy source extension as ratified in version
1.0 of RISC-V Cryptography Extensions Volume I specification.
This string being present means that the CSR associated to this
extension is accessible at the privilege level to which that
device-tree has been provided.
- const: zks
description:
The standard Zks ShangMi algorithm suite extensions as ratified in
version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zksed
description: |
The standard Zksed for ShangMi suite: SM4 block cipher instructions
as ratified in version 1.0 of RISC-V Cryptography Extensions
Volume I specification.
- const: zksh
description: |
The standard Zksh for ShangMi suite: SM3 hash function instructions
as ratified in version 1.0 of RISC-V Cryptography Extensions
Volume I specification.
- const: zkt
description:
The standard Zkt for data independent execution latency as ratified
in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- const: zicbom
description:
The standard Zicbom extension for base cache management operations as
@ -246,6 +351,12 @@ properties:
The standard Zihintpause extension for pause hints, as ratified in
commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
- const: zihintntl
description:
The standard Zihintntl extension for non-temporal locality hints, as
ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
riscv-isa-manual.
- const: zihpm
description:
The standard Zihpm extension for hardware performance counters, as
@ -258,5 +369,113 @@ properties:
in commit 2e5236 ("Ztso is now ratified.") of the
riscv-isa-manual.
- const: zvbb
description:
The standard Zvbb extension for vectored basic bit-manipulation
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvbc
description:
The standard Zvbc extension for vectored carryless multiplication
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvfh
description:
The standard Zvfh extension for vectored half-precision
floating-point instructions, as ratified in commit e2ccd05
("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
- const: zvfhmin
description:
The standard Zvfhmin extension for vectored minimal half-precision
floating-point instructions, as ratified in commit e2ccd05
("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
- const: zvkb
description:
The standard Zvkb extension for vector cryptography bit-manipulation
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvkg
description:
The standard Zvkg extension for vector GCM/GMAC instructions, as
ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
of riscv-crypto.
- const: zvkn
description:
The standard Zvkn extension for NIST algorithm suite instructions, as
ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
of riscv-crypto.
- const: zvknc
description:
The standard Zvknc extension for NIST algorithm suite with carryless
multiply instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvkned
description:
The standard Zvkned extension for Vector AES block cipher
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvkng
description:
The standard Zvkng extension for NIST algorithm suite with GCM
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvknha
description: |
The standard Zvknha extension for NIST suite: vector SHA-2 secure,
hash (SHA-256 only) instructions, as ratified in commit
56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvknhb
description: |
The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
hash (SHA-256 and SHA-512) instructions, as ratified in commit
56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvks
description:
The standard Zvks extension for ShangMi algorithm suite
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvksc
description:
The standard Zvksc extension for ShangMi algorithm suite with
carryless multiplication instructions, as ratified in commit 56ed795
("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvksed
description: |
The standard Zvksed extension for ShangMi suite: SM4 block cipher
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvksh
description: |
The standard Zvksh extension for ShangMi suite: SM3 secure hash
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvksg
description:
The standard Zvksg extension for ShangMi algorithm suite with GCM
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- const: zvkt
description:
The standard Zvkt extension for vector data-independent execution
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
additionalProperties: true
...

57
Documentation/sphinx/kernel_feat.py
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@ -37,8 +37,6 @@ import re
import subprocess
import sys
from os import path
from docutils import nodes, statemachine
from docutils.statemachine import ViewList
from docutils.parsers.rst import directives, Directive
@ -76,33 +74,26 @@ class KernelFeat(Directive):
self.state.document.settings.env.app.warn(message, prefix="")
def run(self):
doc = self.state.document
if not doc.settings.file_insertion_enabled:
raise self.warning("docutils: file insertion disabled")
env = doc.settings.env
cwd = path.dirname(doc.current_source)
cmd = "get_feat.pl rest --enable-fname --dir "
cmd += self.arguments[0]
srctree = os.path.abspath(os.environ["srctree"])
args = [
os.path.join(srctree, 'scripts/get_feat.pl'),
'rest',
'--enable-fname',
'--dir',
os.path.join(srctree, 'Documentation', self.arguments[0]),
]
if len(self.arguments) > 1:
cmd += " --arch " + self.arguments[1]
args.extend(['--arch', self.arguments[1]])
srctree = path.abspath(os.environ["srctree"])
fname = cmd
# extend PATH with $(srctree)/scripts
path_env = os.pathsep.join([
srctree + os.sep + "scripts",
os.environ["PATH"]
])
shell_env = os.environ.copy()
shell_env["PATH"] = path_env
shell_env["srctree"] = srctree
lines = self.runCmd(cmd, shell=True, cwd=cwd, env=shell_env)
lines = subprocess.check_output(args, cwd=os.path.dirname(doc.current_source)).decode('utf-8')
line_regex = re.compile(r"^\.\. FILE (\S+)$")
@ -121,30 +112,6 @@ class KernelFeat(Directive):
nodeList = self.nestedParse(out_lines, fname)
return nodeList
def runCmd(self, cmd, **kwargs):
u"""Run command ``cmd`` and return its stdout as unicode."""
try:
proc = subprocess.Popen(
cmd
, stdout = subprocess.PIPE
, stderr = subprocess.PIPE
, **kwargs
)
out, err = proc.communicate()
out, err = codecs.decode(out, 'utf-8'), codecs.decode(err, 'utf-8')
if proc.returncode != 0:
raise self.severe(
u"command '%s' failed with return code %d"
% (cmd, proc.returncode)
)
except OSError as exc:
raise self.severe(u"problems with '%s' directive: %s."
% (self.name, ErrorString(exc)))
return out
def nestedParse(self, lines, fname):
content = ViewList()
node = nodes.section()

2
Documentation/sphinx/requirements.txt
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@ -1,4 +1,6 @@
# jinja2>=3.1 is not compatible with Sphinx<4.0
jinja2<3.1
# alabaster>=0.7.14 is not compatible with Sphinx<=3.3
alabaster<0.7.14
Sphinx==2.4.4
pyyaml

3
Documentation/trace/kprobes.rst
View File

@ -4,7 +4,7 @@ Kernel Probes (Kprobes)
:Author: Jim Keniston <jkenisto@us.ibm.com>
:Author: Prasanna S Panchamukhi <prasanna.panchamukhi@gmail.com>
:Author: Masami Hiramatsu <mhiramat@redhat.com>
:Author: Masami Hiramatsu <mhiramat@kernel.org>
.. CONTENTS
@ -321,6 +321,7 @@ architectures:
- mips
- s390
- parisc
- loongarch
Configuring Kprobes
===================

2
Documentation/translations/zh_CN/arch/loongarch/features.rst
View File

@ -5,4 +5,4 @@
:Original: Documentation/arch/loongarch/features.rst
:Translator: Huacai Chen <chenhuacai@loongson.cn>
.. kernel-feat:: $srctree/Documentation/features loongarch
.. kernel-feat:: features loongarch

2
Documentation/translations/zh_CN/arch/mips/features.rst
View File

@ -10,4 +10,4 @@
.. _cn_features:
.. kernel-feat:: $srctree/Documentation/features mips
.. kernel-feat:: features mips

2
Documentation/translations/zh_TW/arch/loongarch/features.rst
View File

@ -5,5 +5,5 @@
:Original: Documentation/arch/loongarch/features.rst
:Translator: Huacai Chen <chenhuacai@loongson.cn>
.. kernel-feat:: $srctree/Documentation/features loongarch
.. kernel-feat:: features loongarch

2
Documentation/translations/zh_TW/arch/mips/features.rst
View File

@ -10,5 +10,5 @@
.. _tw_features:
.. kernel-feat:: $srctree/Documentation/features mips
.. kernel-feat:: features mips

1
MAINTAINERS
View File

@ -18196,6 +18196,7 @@ F: drivers/media/cec/usb/rainshadow/
RALINK MIPS ARCHITECTURE
M: John Crispin <john@phrozen.org>
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
L: linux-mips@vger.kernel.org
S: Maintained
F: arch/mips/ralink

1
arch/arm/Kconfig
View File

@ -35,6 +35,7 @@ config ARM
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
select ARCH_SUPPORTS_ATOMIC_RMW
select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
select ARCH_SUPPORTS_PER_VMA_LOCK
select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_CMPXCHG_LOCKREF
select ARCH_USE_MEMTEST

2
arch/arm/include/asm/pgtable.h
View File

@ -151,6 +151,8 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
#define pgdp_get(pgpd) READ_ONCE(*pgdp)
#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
#define pud_write(pud) pmd_write(__pmd(pud_val(pud)))

1
arch/arm/mach-davinci/Kconfig
View File

@ -11,6 +11,7 @@ menuconfig ARCH_DAVINCI
select PM_GENERIC_DOMAINS_OF if PM && OF
select REGMAP_MMIO
select RESET_CONTROLLER
select PINCTRL
select PINCTRL_SINGLE
if ARCH_DAVINCI

5
arch/arm/mm/dma-mapping.c
View File

@ -859,10 +859,7 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
int i = 0;
int order_idx = 0;
if (array_size <= PAGE_SIZE)
pages = kzalloc(array_size, GFP_KERNEL);
else
pages = vzalloc(array_size);
pages = kvzalloc(array_size, GFP_KERNEL);
if (!pages)
return NULL;

30
arch/arm/mm/fault.c
View File

@ -278,6 +278,35 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
if (!(flags & FAULT_FLAG_USER))
goto lock_mmap;
vma = lock_vma_under_rcu(mm, addr);
if (!vma)
goto lock_mmap;
if (!(vma->vm_flags & vm_flags)) {
vma_end_read(vma);
goto lock_mmap;
}
fault = handle_mm_fault(vma, addr, flags | FAULT_FLAG_VMA_LOCK, regs);
if (!(fault & (VM_FAULT_RETRY | VM_FAULT_COMPLETED)))
vma_end_read(vma);
if (!(fault & VM_FAULT_RETRY)) {
count_vm_vma_lock_event(VMA_LOCK_SUCCESS);
goto done;
}
count_vm_vma_lock_event(VMA_LOCK_RETRY);
/* Quick path to respond to signals */
if (fault_signal_pending(fault, regs)) {
if (!user_mode(regs))
goto no_context;
return 0;
}
lock_mmap:
retry:
vma = lock_mm_and_find_vma(mm, addr, regs);
if (unlikely(!vma)) {
@ -316,6 +345,7 @@ retry:
}
mmap_read_unlock(mm);
done:
/*
* Handle the "normal" case first - VM_FAULT_MAJOR

8
arch/arm/mm/kasan_init.c
View File

@ -28,6 +28,12 @@ static pgd_t tmp_pgd_table[PTRS_PER_PGD] __initdata __aligned(PGD_SIZE);
pmd_t tmp_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
static __init void *kasan_alloc_block_raw(size_t size)
{
return memblock_alloc_try_nid_raw(size, size, __pa(MAX_DMA_ADDRESS),
MEMBLOCK_ALLOC_NOLEAKTRACE, NUMA_NO_NODE);
}
static __init void *kasan_alloc_block(size_t size)
{
return memblock_alloc_try_nid(size, size, __pa(MAX_DMA_ADDRESS),
@ -50,7 +56,7 @@ static void __init kasan_pte_populate(pmd_t *pmdp, unsigned long addr,
if (!pte_none(READ_ONCE(*ptep)))
continue;
p = kasan_alloc_block(PAGE_SIZE);
p = kasan_alloc_block_raw(PAGE_SIZE);
if (!p) {
panic("%s failed to allocate shadow page for address 0x%lx\n",
__func__, addr);

18
arch/arm/vfp/vfpmodule.c
View File

@ -800,6 +800,24 @@ static struct undef_hook neon_support_hook[] = {{
.cpsr_mask = PSR_T_BIT,
.cpsr_val = PSR_T_BIT,
.fn = vfp_support_entry,
}, {
.instr_mask = 0xff000800,
.instr_val = 0xfc000800,
.cpsr_mask = 0,
.cpsr_val = 0,
.fn = vfp_support_entry,
}, {
.instr_mask = 0xff000800,
.instr_val = 0xfd000800,
.cpsr_mask = 0,
.cpsr_val = 0,
.fn = vfp_support_entry,
}, {
.instr_mask = 0xff000800,
.instr_val = 0xfe000800,
.cpsr_mask = 0,
.cpsr_val = 0,
.fn = vfp_support_entry,
}};
static struct undef_hook vfp_support_hook = {

13
arch/microblaze/configs/mmu_defconfig
View File

@ -3,11 +3,9 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_AUDIT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_EXPERT=y
# CONFIG_BASE_FULL is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_EXPERT=y
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1
CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
@ -20,7 +18,6 @@ CONFIG_CMDLINE_FORCE=y
CONFIG_HIGHMEM=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_EFI_PARTITION is not set
CONFIG_CMA=y
@ -28,6 +25,10 @@ CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_IPV6 is not set
CONFIG_BRIDGE=m
CONFIG_PCI=y
@ -43,6 +44,7 @@ CONFIG_NETDEVICES=y
CONFIG_XILINX_EMACLITE=y
CONFIG_XILINX_AXI_EMAC=y
CONFIG_XILINX_LL_TEMAC=y
CONFIG_MARVELL_PHY=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
@ -77,14 +79,13 @@ CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_CIFS=y
CONFIG_CIFS_STATS2=y
CONFIG_ENCRYPTED_KEYS=y
CONFIG_DMA_CMA=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_KGDB=y
CONFIG_KGDB_TESTS=y
CONFIG_KGDB_KDB=y
CONFIG_DEBUG_SLAB=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_SPINLOCK=y

2
arch/mips/alchemy/devboards/db1200.c
View File

@ -847,7 +847,7 @@ int __init db1200_dev_setup(void)
i2c_register_board_info(0, db1200_i2c_devs,
ARRAY_SIZE(db1200_i2c_devs));
spi_register_board_info(db1200_spi_devs,
ARRAY_SIZE(db1200_i2c_devs));
ARRAY_SIZE(db1200_spi_devs));
/* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
* S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)

2
arch/mips/alchemy/devboards/db1550.c
View File

@ -589,7 +589,7 @@ int __init db1550_dev_setup(void)
i2c_register_board_info(0, db1550_i2c_devs,
ARRAY_SIZE(db1550_i2c_devs));
spi_register_board_info(db1550_spi_devs,
ARRAY_SIZE(db1550_i2c_devs));
ARRAY_SIZE(db1550_spi_devs));
c = clk_get(NULL, "psc0_intclk");
if (!IS_ERR(c)) {

6
arch/mips/bcm47xx/buttons.c
View File

@ -147,21 +147,21 @@ static const struct gpio_keys_button
bcm47xx_buttons_buffalo_whr_g125[] __initconst = {
BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
BCM47XX_GPIO_KEY(4, KEY_RESTART),
BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
};
static const struct gpio_keys_button
bcm47xx_buttons_buffalo_whr_g54s[] __initconst = {
BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
BCM47XX_GPIO_KEY_H(4, KEY_RESTART),
BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
};
static const struct gpio_keys_button
bcm47xx_buttons_buffalo_whr_hp_g54[] __initconst = {
BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
BCM47XX_GPIO_KEY(4, KEY_RESTART),
BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */
};
static const struct gpio_keys_button

4
arch/mips/bcm63xx/clk.c
View File

@ -174,7 +174,7 @@ static void enetsw_set(struct clk *clk, int enable)
}
if (enable) {
/* reset switch core afer clock change */
/* reset switch core after clock change */
bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
msleep(10);
bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
@ -304,7 +304,7 @@ static void xtm_set(struct clk *clk, int enable)
bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
if (enable) {
/* reset sar core afer clock change */
/* reset sar core after clock change */
bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
mdelay(1);
bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);

2
arch/mips/boot/compressed/dbg.c
View File

@ -3,7 +3,7 @@
* MIPS-specific debug support for pre-boot environment
*
* NOTE: putc() is board specific, if your board have a 16550 compatible uart,
* please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
* please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. otherwise, you
* need to implement your own putc().
*/
#include <linux/compiler.h>

4
arch/mips/boot/compressed/head.S
View File

@ -25,8 +25,8 @@
/* Clear BSS */
PTR_LA a0, _edata
PTR_LA a2, _end
1: sw zero, 0(a0)
addiu a0, a0, 4
1: PTR_S zero, 0(a0)
PTR_ADDIU a0, a0, PTRSIZE
bne a2, a0, 1b
PTR_LA a0, (.heap) /* heap address */

2
arch/mips/boot/elf2ecoff.c
View File

@ -443,7 +443,7 @@ int main(int argc, char *argv[])
efh.f_symptr = 0;
efh.f_nsyms = 0;
efh.f_opthdr = sizeof eah;
efh.f_flags = 0x100f; /* Stripped, not sharable. */
efh.f_flags = 0x100f; /* Stripped, not shareable. */
memset(esecs, 0, sizeof esecs);
strcpy(esecs[0].s_name, ".text");

2
arch/mips/cavium-octeon/csrc-octeon.c
View File

@ -113,7 +113,7 @@ static struct clocksource clocksource_mips = {
unsigned long long notrace sched_clock(void)
{
/* 64-bit arithmatic can overflow, so use 128-bit. */
/* 64-bit arithmetic can overflow, so use 128-bit. */
u64 t1, t2, t3;
unsigned long long rv;
u64 mult = clocksource_mips.mult;

2
arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
View File

@ -143,7 +143,7 @@ static void cvmx_boot_vector_init(void *mem)
uint64_t v = _cvmx_bootvector_data[i];
if (OCTEON_IS_OCTEON1PLUS() && (i == 0 || i == 7))
v &= 0xffffffff00000000ull; /* KScratch not availble. */
v &= 0xffffffff00000000ull; /* KScratch not available */
cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);
}

2
arch/mips/cavium-octeon/executive/cvmx-bootmem.c
View File

@ -264,7 +264,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
* Convert !0 address_min and 0 address_max to special case of
* range that specifies an exact memory block to allocate. Do
* this before other checks and adjustments so that this
* tranformation will be validated.
* transformation will be validated.
*/
if (address_min && !address_max)
address_max = address_min + req_size;

4
arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
View File

@ -192,7 +192,7 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
}
/*
* Shutdown a queue a free it's command buffers to the FPA. The
* Shutdown a queue and free its command buffers to the FPA. The
* hardware connected to the queue must be stopped before this
* function is called.
*
@ -285,7 +285,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
/*
* Return the command buffer to be written to. The purpose of this
* function is to allow CVMX routine access t othe low level buffer
* function is to allow CVMX routine access to the low level buffer
* for initial hardware setup. User applications should not call this
* function directly.
*

2
arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
View File

@ -103,7 +103,7 @@ uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
/**
* Shift long sequences of zeros into the QLM JTAG chain. It is
* common to need to shift more than 32 bits of zeros into the
* chain. This function is a convience wrapper around
* chain. This function is a convenience wrapper around
* cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
* zeros at a time.
*

2
arch/mips/cavium-octeon/executive/cvmx-pko.c
View File

@ -615,7 +615,7 @@ int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
/*
* Each packet has a 12 bytes of interframe gap, an 8 byte
* preamble, and a 4 byte CRC. These are not included in the
* per word count. Multiply by 8 to covert to bits and divide
* per word count. Multiply by 8 to convert to bits and divide
* by 256 for limit granularity.
*/
pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;

2
arch/mips/cavium-octeon/octeon-platform.c
View File

@ -973,7 +973,7 @@ int __init octeon_prune_device_tree(void)
* zero.
*/
/* Asume that CS1 immediately follows. */
/* Assume that CS1 immediately follows. */
mio_boot_reg_cfg.u64 =
cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
region1_base = mio_boot_reg_cfg.s.base << 16;

6
arch/mips/fw/arc/promlib.c
View File

@ -15,11 +15,11 @@
/*
* For 64bit kernels working with a 32bit ARC PROM pointer arguments
* for ARC calls need to reside in CKEG0/1. But as soon as the kernel
* switches to it's first kernel thread stack is set to an address in
* switches to its first kernel thread stack is set to an address in
* XKPHYS, so anything on stack can't be used anymore. This is solved
* by using a * static declartion variables are put into BSS, which is
* by using a * static declaration variables are put into BSS, which is
* linked to a CKSEG0 address. Since this is only used on UP platforms
* there is not spinlock needed
* there is no spinlock needed
*/
#define O32_STATIC static
#else

2
arch/mips/include/asm/debug.h
View File

@ -10,7 +10,7 @@
/*
* mips_debugfs_dir corresponds to the "mips" directory at the top level
* of the DebugFS hierarchy. MIPS-specific DebugFS entires should be
* of the DebugFS hierarchy. MIPS-specific DebugFS entries should be
* placed beneath this directory.
*/
extern struct dentry *mips_debugfs_dir;

2
arch/mips/include/asm/dmi.h
View File

@ -5,7 +5,7 @@
#include <linux/io.h>
#include <linux/memblock.h>
#define dmi_early_remap(x, l) ioremap_cache(x, l)
#define dmi_early_remap(x, l) ioremap(x, l)
#define dmi_early_unmap(x, l) iounmap(x)
#define dmi_remap(x, l) ioremap_cache(x, l)
#define dmi_unmap(x) iounmap(x)

4
arch/mips/include/asm/io.h
View File

@ -159,7 +159,7 @@ void iounmap(const volatile void __iomem *addr);
* address is not guaranteed to be usable directly as a virtual
* address.
*
* This version of ioremap ensures that the memory is marked cachable by
* This version of ioremap ensures that the memory is marked cacheable by
* the CPU. Also enables full write-combining. Useful for some
* memory-like regions on I/O busses.
*/
@ -177,7 +177,7 @@ void iounmap(const volatile void __iomem *addr);
* address is not guaranteed to be usable directly as a virtual
* address.
*
* This version of ioremap ensures that the memory is marked uncachable
* This version of ioremap ensures that the memory is marked uncacheable
* but accelerated by means of write-combining feature. It is specifically
* useful for PCIe prefetchable windows, which may vastly improve a
* communications performance. If it was determined on boot stage, what

2
arch/mips/include/asm/mach-au1x00/au1000_dma.h
View File

@ -259,7 +259,7 @@ static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
if (!chan)
return;
/*
* set_dma_mode is only allowed to change endianess, direction,
* set_dma_mode is only allowed to change endianness, direction,
* transfer size, device FIFO width, and coherency settings.
* Make sure anything else is masked off.
*/

2
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
View File

@ -435,7 +435,7 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
/**
* alchemy_gpio2_enable - Activate GPIO2 block.
*
* The GPIO2 block must be enabled excplicitly to work. On systems
* The GPIO2 block must be enabled explicitly to work. On systems
* where this isn't done by the bootloader, this macro can be used.
*/
static inline void alchemy_gpio2_enable(void)

2
arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
View File

@ -55,7 +55,7 @@ extern __iomem void *ltq_sys1_membase;
#define ltq_sys1_w32_mask(clear, set, reg) \
ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
/* allow the gpio and pinctrl drivers to talk to eachother */
/* allow the gpio and pinctrl drivers to talk to each other */
extern int pinctrl_falcon_get_range_size(int id);
extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);

2
arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
View File

@ -42,7 +42,7 @@ struct loongson_fan_policy {
/* period between two check. (Unit: S) */
u8 adjust_period;
/* fan adjust usually depend on a temprature input */
/* fan adjust usually depend on a temperature input */
get_temp_fun depend_temp;
/* up_step/down_step used when type is STEP_SPEED_POLICY */

2
arch/mips/include/asm/mach-loongson64/loongson_regs.h
View File

@ -227,7 +227,7 @@ static inline void csr_writeq(u64 val, u32 reg)
#define LOONGSON_CSR_NODECNT 0x408
#define LOONGSON_CSR_CPUTEMP 0x428
/* PerCore CSR, only accessable by local cores */
/* PerCore CSR, only accessible by local cores */
#define LOONGSON_CSR_IPI_STATUS 0x1000
#define LOONGSON_CSR_IPI_EN 0x1004
#define LOONGSON_CSR_IPI_SET 0x1008

4
arch/mips/include/asm/mach-malta/spaces.h
View File

@ -23,13 +23,13 @@
* The kernel is still located in 0x80000000(kseg0). However,
* the physical mask has been shifted to 0x80000000 which exploits the alias
* on the Malta board. As a result of which, we override the __pa_symbol
* to peform direct mapping from virtual to physical addresses. In other
* to perform direct mapping from virtual to physical addresses. In other
* words, the 0x80000000 virtual address maps to 0x80000000 physical address
* which in turn aliases to 0x0. We do this in order to be able to use a flat
* 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
* 0x10000000 - 0x1fffffff.
* The last 64KB of physical memory are reserved for correct HIGHMEM
* macros arithmetics.
* macros arithmetic.
*
*/

2
arch/mips/include/asm/mips-boards/bonito64.h
View File

@ -16,7 +16,7 @@
*/
/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
/* This bonito64 version edited from bonito.h Revision 1.48 on 11/09/00 */
#ifndef _ASM_MIPS_BOARDS_BONITO64_H
#define _ASM_MIPS_BOARDS_BONITO64_H

2
arch/mips/include/asm/mips-cpc.h
View File

@ -22,7 +22,7 @@ extern void __iomem *mips_cpc_base;
* the CPC
*
* Returns the default physical base address of the Cluster Power Controller
* memory mapped registers. This is platform dependant & must therefore be
* memory mapped registers. This is platform dependent & must therefore be
* implemented per-platform.
*/
extern phys_addr_t mips_cpc_default_phys_base(void);

4
arch/mips/include/asm/mipsregs.h
View File

@ -98,7 +98,7 @@
/*
* R4640/R4650 cp0 register names. These registers are listed
* here only for completeness; without MMU these CPUs are not useable
* here only for completeness; without MMU these CPUs are not usable
* by Linux. A future ELKS port might take make Linux run on them
* though ...
*/
@ -461,7 +461,7 @@
#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
#define EXCCODE_CACHEERR 30 /* Parity/ECC occured on a core */
#define EXCCODE_CACHEERR 30 /* Parity/ECC occurred on a core */
/* Implementation specific trap codes used by MIPS cores */
#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */

2
arch/mips/include/asm/octeon/cvmx-bootinfo.h
View File

@ -114,7 +114,7 @@ struct cvmx_bootinfo {
/*
* flags indicating various configuration options. These
* flags supercede the 'flags' variable and should be used
* flags supersede the 'flags' variable and should be used
* instead if available.
*/
uint32_t config_flags;

6
arch/mips/include/asm/octeon/cvmx-cmd-queue.h
View File

@ -145,7 +145,7 @@ typedef struct {
/**
* This structure contains the global state of all command queues.
* It is stored in a bootmem named block and shared by all
* applications running on Octeon. Tickets are stored in a differnet
* applications running on Octeon. Tickets are stored in a different
* cache line that queue information to reduce the contention on the
* ll/sc used to get a ticket. If this is not the case, the update
* of queue state causes the ll/sc to fail quite often.
@ -172,7 +172,7 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
int pool_size);
/**
* Shutdown a queue a free it's command buffers to the FPA. The
* Shutdown a queue and free its command buffers to the FPA. The
* hardware connected to the queue must be stopped before this
* function is called.
*
@ -194,7 +194,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
/**
* Return the command buffer to be written to. The purpose of this
* function is to allow CVMX routine access t othe low level buffer
* function is to allow CVMX routine access to the low level buffer
* for initial hardware setup. User applications should not call this
* function directly.
*

2
arch/mips/include/asm/octeon/cvmx-pko.h
View File

@ -91,7 +91,7 @@ typedef enum {
} cvmx_pko_status_t;
/**
* This enumeration represents the differnet locking modes supported by PKO.
* This enumeration represents the different locking modes supported by PKO.
*/
typedef enum {
/*

4
arch/mips/include/asm/octeon/cvmx-pow.h
View File

@ -1342,7 +1342,7 @@ static inline void cvmx_pow_tag_sw_wait(void)
* This function does NOT wait for previous tag switches to complete,
* so the caller must ensure that there is not a pending tag switch.
*
* @wait: When set, call stalls until work becomes avaiable, or times out.
* @wait: When set, call stalls until work becomes available, or times out.
* If not set, returns immediately.
*
* Returns: the WQE pointer from POW. Returns NULL if no work
@ -1376,7 +1376,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_
* This function waits for any previous tag switch to complete before
* requesting the new work.
*
* @wait: When set, call stalls until work becomes avaiable, or times out.
* @wait: When set, call stalls until work becomes available, or times out.
* If not set, returns immediately.
*
* Returns: the WQE pointer from POW. Returns NULL if no work

4
arch/mips/include/asm/octeon/octeon-model.h
View File

@ -54,7 +54,7 @@
#define OM_CHECK_SUBMODEL 0x02000000
/* Match all models previous than the one specified */
#define OM_MATCH_PREVIOUS_MODELS 0x04000000
/* Ignores the minor revison on newer parts */
/* Ignores the minor revision on newer parts */
#define OM_IGNORE_MINOR_REVISION 0x08000000
#define OM_FLAG_MASK 0xff000000
@ -226,7 +226,7 @@
#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
/*
* CN3XXX models with old revision enconding
* CN3XXX models with old revision encoding
*/
#define OCTEON_CN38XX_PASS1 0x000d0000
#define OCTEON_CN38XX_PASS2 0x000d0001

2
arch/mips/include/asm/page.h
View File

@ -173,7 +173,7 @@ static inline unsigned long ___pa(unsigned long x)
if (IS_ENABLED(CONFIG_64BIT)) {
/*
* For MIPS64 the virtual address may either be in one of
* the compatibility segements ckseg0 or ckseg1, or it may
* the compatibility segments ckseg0 or ckseg1, or it may
* be in xkphys.
*/
return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);

2
arch/mips/include/asm/pci.h
View File

@ -23,7 +23,7 @@
#ifdef CONFIG_PCI_DRIVERS_LEGACY
/*
* Each pci channel is a top-level PCI bus seem by CPU. A machine with
* Each PCI channel is a top-level PCI bus seem by CPU. A machine with
* multiple PCI channels may have multiple PCI host controllers or a
* single controller supporting multiple channels.
*/

2
arch/mips/include/asm/pgtable-bits.h
View File

@ -201,7 +201,7 @@ enum pgtable_bits {
* The final layouts of the PTE bits are:
*
* 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
* 32-bit, R1 or earler: CCC D V G M A W R P
* 32-bit, R1 or earlier: CCC D V G M A W R P
* 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
* 32-bit, R2 or later: CCC D V G RI/R XI M A W P
*/

2
arch/mips/include/asm/sgi/mc.h
View File

@ -96,7 +96,7 @@ struct sgimc_regs {
volatile u32 lbursttp; /* Time period for long bursts */
/* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
* be the same size. The size encoding for supported SIMMs is bellow */
* be the same size. The size encoding for supported SIMMs is below */
u32 _unused11[9];
volatile u32 mconfig0; /* Memory config register zero */
u32 _unused12;

2
arch/mips/include/asm/sn/klconfig.h
View File

@ -851,7 +851,7 @@ typedef union kldev_s { /* for device structure allocation */
/*
* TBD - Allocation issues.
*
* Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
* Do we need to Mark off separate heaps for lboard_t, rboard_t, component,
* errinfo and allocate from them, or have a single heap and allocate all
* structures from it. Debug is easier in the former method since we can
* dump all similar structs in one command, but there will be lots of holes,

2
arch/mips/include/asm/sync.h
View File

@ -19,7 +19,7 @@
*
* Ordering barriers can be more efficient than completion barriers, since:
*
* a) Ordering barriers only require memory access instructions which preceed
* a) Ordering barriers only require memory access instructions which precede
* them in program order (older instructions) to reach a point in the
* load/store datapath beyond which reordering is not possible before
* allowing memory access instructions which follow them (younger

2
arch/mips/include/asm/thread_info.h
View File

@ -27,7 +27,7 @@ struct thread_info {
unsigned long flags; /* low level flags */
unsigned long tp_value; /* thread pointer */
__u32 cpu; /* current CPU */
int preempt_count; /* 0 => preemptable, <0 => BUG */
int preempt_count; /* 0 => preemptible, <0 => BUG */
struct pt_regs *regs;
long syscall; /* syscall number */
};

2
arch/mips/include/asm/timex.h
View File

@ -46,7 +46,7 @@ typedef unsigned int cycles_t;
*
* There is a suggested workaround and also the erratum can't strike if
* the compare interrupt isn't being used as the clock source device.
* However for now the implementaton of this function doesn't get these
* However for now the implementation of this function doesn't get these
* fine details right.
*/
static inline int can_use_mips_counter(unsigned int prid)

2
arch/mips/include/asm/vdso/vdso.h
View File

@ -32,7 +32,7 @@ static inline unsigned long get_vdso_base(void)
#else
/*
* Get the base load address of the VDSO. We have to avoid generating
* relocations and references to the GOT because ld.so does not peform
* relocations and references to the GOT because ld.so does not perform
* relocations on the VDSO. We use the current offset from the VDSO base
* and perform a PC-relative branch which gives the absolute address in
* ra, and take the difference. The assembler chokes on

2
arch/mips/include/uapi/asm/mman.h
View File

@ -88,7 +88,7 @@
#define MADV_HUGEPAGE 14 /* Worth backing with hugepages */
#define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages */
#define MADV_DONTDUMP 16 /* Explicity exclude from the core dump,
#define MADV_DONTDUMP 16 /* Explicitly exclude from core dump,
overrides the coredump filter bits */
#define MADV_DODUMP 17 /* Clear the MADV_NODUMP flag */

2
arch/mips/include/uapi/asm/msgbuf.h
View File

@ -62,7 +62,7 @@ struct msqid64_ds {
unsigned long __unused5;
};
#else
#warning no endianess set
#warning no endianness set
#endif
#endif /* _ASM_MSGBUF_H */

2
arch/mips/kernel/cpu-probe.c
View File

@ -1138,7 +1138,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
* This processor doesn't have an MMU, so it's not
* "real easy" to run Linux on it. It is left purely
* for documentation. Commented out because it shares
* it's c0_prid id number with the TX3900.
* its c0_prid id number with the TX3900.
*/
c->cputype = CPU_R4650;
__cpu_name[cpu] = "R4650";

8
arch/mips/kernel/genex.S
View File

@ -272,18 +272,17 @@ NESTED(except_vec_vi, 0, sp)
.set push
.set noreorder
PTR_LA v1, except_vec_vi_handler
FEXPORT(except_vec_vi_lui)
lui v0, 0 /* Patched */
jr v1
FEXPORT(except_vec_vi_ori)
ori v0, 0 /* Patched */
ori v0, zero, 0 /* Offset in vi_handlers[] */
.set pop
END(except_vec_vi)
EXPORT(except_vec_vi_end)
/*
* Common Vectored Interrupt code
* Complete the register saves and invoke the handler which is passed in $v0
* Complete the register saves and invoke the handler, $v0 holds
* offset into vi_handlers[]
*/
NESTED(except_vec_vi_handler, 0, sp)
SAVE_TEMP
@ -331,6 +330,7 @@ NESTED(except_vec_vi_handler, 0, sp)
/* Save task's sp on IRQ stack so that unwinding can follow it */
LONG_S s1, 0(sp)
2:
PTR_L v0, vi_handlers(v0)
jalr v0
/* Restore sp */

2
arch/mips/kernel/kprobes.c
View File

@ -55,7 +55,7 @@ NOKPROBE_SYMBOL(insn_has_delayslot);
* one; putting breakpoint on top of atomic ll/sc pair is bad idea;
* so we need to prevent it and refuse kprobes insertion for such
* instructions; cannot do much about breakpoint in the middle of
* ll/sc pair; it is upto user to avoid those places
* ll/sc pair; it is up to user to avoid those places
*/
static int insn_has_ll_or_sc(union mips_instruction insn)
{

2
arch/mips/kernel/prom.c
View File

@ -28,6 +28,8 @@ __init void mips_set_machine_name(const char *name)
strscpy(mips_machine_name, name, sizeof(mips_machine_name));
pr_info("MIPS: machine is %s\n", mips_get_machine_name());
dump_stack_set_arch_desc(name);
}
char *mips_get_machine_name(void)

2
arch/mips/kernel/relocate.c
View File

@ -380,7 +380,7 @@ void *__init relocate_kernel(void)
}
#endif /* CONFIG_USE_OF */
/* Copy the kernel to it's new location */
/* Copy the kernel to its new location */
memcpy(loc_new, &_text, kernel_length);
/* Perform relocations on the new kernel */

2
arch/mips/kernel/relocate_kernel.S
View File

@ -70,7 +70,7 @@ copy_word:
done:
#ifdef CONFIG_SMP
/* kexec_flag reset is signal to other CPUs what kernel
was moved to it's location. Note - we need relocated address
was moved to its location. Note - we need relocated address
of kexec_flag. */
bal 1f

6
arch/mips/kernel/setup.c
View File

@ -147,7 +147,7 @@ static unsigned long __init init_initrd(void)
/*
* Board specific code or command line parser should have
* already set up initrd_start and initrd_end. In these cases
* perfom sanity checks and use them if all looks good.
* perform sanity checks and use them if all looks good.
*/
if (!initrd_start || initrd_end <= initrd_start)
goto disable;
@ -322,11 +322,11 @@ static void __init bootmem_init(void)
panic("Incorrect memory mapping !!!");
if (max_pfn > PFN_DOWN(HIGHMEM_START)) {
max_low_pfn = PFN_DOWN(HIGHMEM_START);
#ifdef CONFIG_HIGHMEM
highstart_pfn = PFN_DOWN(HIGHMEM_START);
highstart_pfn = max_low_pfn;
highend_pfn = max_pfn;
#else
max_low_pfn = PFN_DOWN(HIGHMEM_START);
max_pfn = max_low_pfn;
#endif
}

2
arch/mips/kernel/signal.c
View File

@ -570,7 +570,7 @@ void __user *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
return (void __user __force *)(-1UL);
/*
* FPU emulator may have it's own trampoline active just
* FPU emulator may have its own trampoline active just
* above the user stack, 16-bytes before the next lowest
* 16 byte boundary. Try to avoid trashing it.
*/

99
arch/mips/kernel/traps.c
View File

@ -2055,108 +2055,71 @@ static void do_default_vi(void)
panic("Caught unexpected vectored interrupt.");
}
static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
void *set_vi_handler(int n, vi_handler_t addr)
{
extern const u8 except_vec_vi[];
extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
extern const u8 rollback_except_vec_vi[];
unsigned long handler;
unsigned long old_handler = vi_handlers[n];
int srssets = current_cpu_data.srsets;
u16 *h;
unsigned char *b;
const u8 *vec_start;
int ori_offset;
int handler_len;
BUG_ON(!cpu_has_veic && !cpu_has_vint);
if (addr == NULL) {
handler = (unsigned long) do_default_vi;
srs = 0;
} else
handler = (unsigned long) addr;
vi_handlers[n] = handler;
b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
if (srs >= srssets)
panic("Shadow register set %d not supported", srs);
if (cpu_has_veic) {
if (board_bind_eic_interrupt)
board_bind_eic_interrupt(n, srs);
board_bind_eic_interrupt(n, 0);
} else if (cpu_has_vint) {
/* SRSMap is only defined if shadow sets are implemented */
if (srssets > 1)
change_c0_srsmap(0xf << n*4, srs << n*4);
change_c0_srsmap(0xf << n*4, 0 << n*4);
}
if (srs == 0) {
/*
* If no shadow set is selected then use the default handler
* that does normal register saving and standard interrupt exit
*/
extern const u8 except_vec_vi[], except_vec_vi_lui[];
extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
extern const u8 rollback_except_vec_vi[];
const u8 *vec_start = using_rollback_handler() ?
rollback_except_vec_vi : except_vec_vi;
vec_start = using_rollback_handler() ? rollback_except_vec_vi :
except_vec_vi;
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
const int lui_offset = except_vec_vi_lui - vec_start + 2;
const int ori_offset = except_vec_vi_ori - vec_start + 2;
ori_offset = except_vec_vi_ori - vec_start + 2;
#else
const int lui_offset = except_vec_vi_lui - vec_start;
const int ori_offset = except_vec_vi_ori - vec_start;
ori_offset = except_vec_vi_ori - vec_start;
#endif
const int handler_len = except_vec_vi_end - vec_start;
handler_len = except_vec_vi_end - vec_start;
if (handler_len > VECTORSPACING) {
/*
* Sigh... panicing won't help as the console
* is probably not configured :(
*/
panic("VECTORSPACING too small");
}
set_handler(((unsigned long)b - ebase), vec_start,
#ifdef CONFIG_CPU_MICROMIPS
(handler_len - 1));
#else
handler_len);
#endif
h = (u16 *)(b + lui_offset);
*h = (handler >> 16) & 0xffff;
h = (u16 *)(b + ori_offset);
*h = (handler & 0xffff);
local_flush_icache_range((unsigned long)b,
(unsigned long)(b+handler_len));
}
else {
if (handler_len > VECTORSPACING) {
/*
* In other cases jump directly to the interrupt handler. It
* is the handler's responsibility to save registers if required
* (eg hi/lo) and return from the exception using "eret".
* Sigh... panicing won't help as the console
* is probably not configured :(
*/
u32 insn;
h = (u16 *)b;
/* j handler */
#ifdef CONFIG_CPU_MICROMIPS
insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
#else
insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
#endif
h[0] = (insn >> 16) & 0xffff;
h[1] = insn & 0xffff;
h[2] = 0;
h[3] = 0;
local_flush_icache_range((unsigned long)b,
(unsigned long)(b+8));
panic("VECTORSPACING too small");
}
set_handler(((unsigned long)b - ebase), vec_start,
#ifdef CONFIG_CPU_MICROMIPS
(handler_len - 1));
#else
handler_len);
#endif
/* insert offset into vi_handlers[] */
h = (u16 *)(b + ori_offset);
*h = n * sizeof(handler);
local_flush_icache_range((unsigned long)b,
(unsigned long)(b+handler_len));
return (void *)old_handler;
}
void *set_vi_handler(int n, vi_handler_t addr)
{
return set_vi_srs_handler(n, addr, 0);
}
/*
* Timer interrupt
*/
@ -2416,7 +2379,7 @@ void __init trap_init(void)
set_except_vector(i, handle_reserved);
/*
* Copy the EJTAG debug exception vector handler code to it's final
* Copy the EJTAG debug exception vector handler code to its final
* destination.
*/
if (cpu_has_ejtag && board_ejtag_handler_setup)

4
arch/mips/kernel/vpe.c
View File

@ -6,9 +6,9 @@
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2013 Imagination Technologies Ltd.
*
* VPE spport module for loading a MIPS SP program into VPE1. The SP
* VPE support module for loading a MIPS SP program into VPE1. The SP
* environment is rather simple since there are no TLBs. It needs
* to be relocatable (or partiall linked). Initialize your stack in
* to be relocatable (or partially linked). Initialize your stack in
* the startup-code. The loader looks for the symbol __start and sets
* up the execution to resume from there. To load and run, simply do
* a cat SP 'binary' to the /dev/vpe1 device.

2
arch/mips/kvm/emulate.c
View File

@ -531,7 +531,7 @@ static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
* to be used for a period of time, but the exact ktime corresponding to the
* final Count that must be restored is not known.
*
* It is gauranteed that a timer interrupt immediately after restore will be
* It is guaranteed that a timer interrupt immediately after restore will be
* handled, but not if CP0_Compare is exactly at @count. That case should
* already be handled when the hardware timer state is saved.
*

2
arch/mips/loongson2ef/common/platform.c
View File

@ -17,7 +17,7 @@ static int __init loongson2_cpufreq_init(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
/* Only 2F revision and it's successors support CPUFreq */
/* Only 2F revision and its successors support CPUFreq */
if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
return platform_device_register(&loongson2_cpufreq_device);

2
arch/mips/loongson64/smp.c
View File

@ -516,7 +516,7 @@ static void __init loongson3_prepare_cpus(unsigned int max_cpus)
}
/*
* Setup the PC, SP, and GP of a secondary processor and start it runing!
* Setup the PC, SP, and GP of a secondary processor and start it running!
*/
static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
{

2
arch/mips/mm/c-r4k.c
View File

@ -1650,7 +1650,7 @@ static void coherency_setup(void)
/*
* c0_status.cu=0 specifies that updates by the sc instruction use
* the coherency mode specified by the TLB; 1 means cachable
* the coherency mode specified by the TLB; 1 means cacheable
* coherent update on write will be used. Not all processors have
* this bit and; some wire it to zero, others like Toshiba had the
* silly idea of putting something else there ...

2
arch/mips/mm/cex-gen.S
View File

@ -25,7 +25,7 @@
* This is a very bad place to be. Our cache error
* detection has triggered. If we have write-back data
* in the cache, we may not be able to recover. As a
* first-order desperate measure, turn off KSEG0 cacheing.
* first-order desperate measure, turn off KSEG0 caching.
*/
mfc0 k0,CP0_CONFIG
li k1,~CONF_CM_CMASK

16
arch/mips/mm/init.c
View File

@ -422,8 +422,17 @@ void __init paging_init(void)
" %ldk highmem ignored\n",
(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
max_mapnr = max_low_pfn;
} else if (highend_pfn) {
max_mapnr = highend_pfn;
} else {
max_mapnr = max_low_pfn;
}
#else
max_mapnr = max_low_pfn;
#endif
high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
free_area_init(max_zone_pfns);
}
@ -459,13 +468,6 @@ void __init mem_init(void)
*/
BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (PFN_PTE_SHIFT > PAGE_SHIFT));
#ifdef CONFIG_HIGHMEM
max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
#else
max_mapnr = max_low_pfn;
#endif
high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
maar_init();
memblock_free_all();
setup_zero_pages(); /* Setup zeroed pages. */

4
arch/mips/mm/ioremap.c
View File

@ -72,6 +72,10 @@ void __iomem *ioremap_prot(phys_addr_t phys_addr, unsigned long size,
flags == _CACHE_UNCACHED)
return (void __iomem *) CKSEG1ADDR(phys_addr);
/* Early remaps should use the unmapped regions til' VM is available */
if (WARN_ON_ONCE(!slab_is_available()))
return NULL;
/*
* Don't allow anybody to remap RAM that may be allocated by the page
* allocator, since that could lead to races & data clobbering.

2
arch/mips/mm/tlb-r3k.c
View File

@ -183,7 +183,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
int idx, pid;
/*
* Handle debugger faulting in for debugee.
* Handle debugger faulting in for debuggee.
*/
if (current->active_mm != vma->vm_mm)
return;

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