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ARM: tegra: dt: add L2 cache controller

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Add L2 cache controller binding into DT for Tegra.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Joseph Lo 2012-10-29 18:25:45 +08:00 committed by Stephen Warren
parent d534b5d4a5
commit 5ab134ad09
2 changed files with 18 additions and 0 deletions
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9
arch/arm/boot/dts/tegra20.dtsi
View File

@ -4,6 +4,15 @@
compatible = "nvidia,tegra20";
interrupt-parent = <&intc>;
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <5 5 2>;
arm,tag-latency = <4 4 2>;
cache-unified;
cache-level = <2>;
};
intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000

9
arch/arm/boot/dts/tegra30.dtsi
View File

@ -4,6 +4,15 @@
compatible = "nvidia,tegra30";
interrupt-parent = <&intc>;
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <6 6 2>;
arm,tag-latency = <5 5 2>;
cache-unified;
cache-level = <2>;
};
intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000