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intel-pinctrl for v6.3-1

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* Add ~4kOhm bias support to Intel pin control drivers
 * Convert Intel pin control drivers to use INTEL_COMMUNITY_*()
 * Add struct pinfunction and use it in Intel pin control drivers
 * Make pin control documentation up to date
 * Miscellaneous cleanups
 
 The following is an automated git shortlog grouped by driver:
 
 pinctrl:
  - Proofreading and updating the documentation accordingly
  - Proofreading and updating the documentation (part 2)
 
 alderlake:
  -  Replace ADL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 baytrail:
  -  Convert to use new memeber in struct intel_function
 
 broxton:
  -  Replace BXT_COMMUNITY() by INTEL_COMMUNITY_SIZE()
 
 cannonlake:
  -  Replace CNL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 cedarfork:
  -  Replace CDF_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 cherryview:
  -  Convert to use new memeber in struct intel_function
 
 denverton:
  -  Replace DNV_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 elkhartlake:
  -  Replace EHL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 emmitsburg:
  -  Replace EBG_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 geminilake:
  -  Replace GLK_COMMUNITY() by INTEL_COMMUNITY_SIZE()
 
 icelake:
  -  Replace ICL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 intel:
  -  Get rid of unused members in struct intel_function
  -  Make use of struct pinfunction and PINCTRL_PINFUNCTION()
  -  Define maximum pad number in the group
  -  Use same order of bit fields for PADCFG2
  -  Add ~4k bias support
  -  Add definitions to all possible biases
  -  Deduplicate some code in intel_config_set_pull()
  -  Add default case to intel_config_set_pull()
  -  Convert to generic_handle_domain_irq()
  -  Always use gpp_num_padown_regs in the main driver
  -  Introduce INTEL_COMMUNITY_*() to unify community macros
 
 Introduce struct pinfunction and PINCTRL_PINFUNCTION() macro:
  - Introduce struct pinfunction and PINCTRL_PINFUNCTION() macro
 
 jasperlake:
  -  Replace JSL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 lakefield:
  -  Replace LKF_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 lewisburg:
  -  Replace LBG_COMMUNITY() by INTEL_COMMUNITY_SIZE()
 
 lynxpoint:
  -  Convert to use new memeber in struct intel_function
 
 merrifield:
  -  Convert to use new memeber in struct intel_function
 
 meteorlake:
  -  Replace MTL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 
 moorefield:
  -  Convert to use new memeber in struct intel_function
 
 sunrisepoint:
  -  Replace SPT_COMMUNITY() by INTEL_COMMUNITY_*()
 
 tigerlake:
  -  Replace TGL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmPYCVAACgkQb7wzTHR8
 rCgn8g//csD+K8oI/IvvY61EiTO/3P+tBgVSphKGgxeVPVJ28nSkqSXaCp7PzgOq
 IWKxfjIzX0IHtJ9Kdm0+P0966FzGz9dS1wo9yIW8/z5ZJ63RStRqW72Kg+99dC+w
 T1k+JwqUY/qYYEqkYlOV2QzTNCAjDLKokI6gReSvsDeLJw7r9RMkh3xjYRieuIPE
 g3anUadyVY7IEPJ/Jt1b6veolAV7vZmYO7fRzoXlhYh+KijSAqAKb16nygl1u1AR
 BN1Db8rSIYFPdhMl2b/JEywCf2GO25DYDjczHt5tffzMNgFvbWce8CmQLYvXm7oR
 303GM1tBY6ACgRzSIw9R7+1MRpCz90ftimK48HGq+6Gr93eJ+87OAwZMJf7pZktN
 xCF73hqkXxIG9p47qhnAsg4StWqpkT7/YpicBwoRWqVx4gAhXxtVesO3bpB2C3Eg
 8u+Fpmo2lTIxepRXsemDaMfRfJxk/bChiVGls7FLHHPgQfKuuaSMcApvx0FyWDen
 m4AJ8tuWJ7mbOpzZUbaUb3zi1vpdrNmucf56YLjHS24zGgq1dha5iBwRDAYHOUgf
 t5OiiYtVMNlUvFbL/yWlrc/bUxs2lqlzUhWAj+ixopP9bIAVMHz2i+vResgNcFI5
 fRnSkZszV3kEltiEGD3iyeplp5rE9Ijdpkwde2KhMR7zmbPdDx0=
 =ZLEJ
 -----END PGP SIGNATURE-----

Merge tag 'intel-pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v6.3-1

* Add ~4kOhm bias support to Intel pin control drivers
* Convert Intel pin control drivers to use INTEL_COMMUNITY_*()
* Add struct pinfunction and use it in Intel pin control drivers
* Make pin control documentation up to date
* Miscellaneous cleanups

The following is an automated git shortlog grouped by driver:

pinctrl:
 - Proofreading and updating the documentation accordingly
 - Proofreading and updating the documentation (part 2)

alderlake:
 -  Replace ADL_COMMUNITY() by INTEL_COMMUNITY_GPPS()

baytrail:
 -  Convert to use new memeber in struct intel_function

broxton:
 -  Replace BXT_COMMUNITY() by INTEL_COMMUNITY_SIZE()

cannonlake:
 -  Replace CNL_COMMUNITY() by INTEL_COMMUNITY_GPPS()

cedarfork:
 -  Replace CDF_COMMUNITY() by INTEL_COMMUNITY_GPPS()

cherryview:
 -  Convert to use new memeber in struct intel_function

denverton:
 -  Replace DNV_COMMUNITY() by INTEL_COMMUNITY_GPPS()

elkhartlake:
 -  Replace EHL_COMMUNITY() by INTEL_COMMUNITY_GPPS()

emmitsburg:
 -  Replace EBG_COMMUNITY() by INTEL_COMMUNITY_GPPS()

geminilake:
 -  Replace GLK_COMMUNITY() by INTEL_COMMUNITY_SIZE()

icelake:
 -  Replace ICL_COMMUNITY() by INTEL_COMMUNITY_GPPS()

intel:
 -  Get rid of unused members in struct intel_function
 -  Make use of struct pinfunction and PINCTRL_PINFUNCTION()
 -  Define maximum pad number in the group
 -  Use same order of bit fields for PADCFG2
 -  Add ~4k bias support
 -  Add definitions to all possible biases
 -  Deduplicate some code in intel_config_set_pull()
 -  Add default case to intel_config_set_pull()
 -  Convert to generic_handle_domain_irq()
 -  Always use gpp_num_padown_regs in the main driver
 -  Introduce INTEL_COMMUNITY_*() to unify community macros

Introduce struct pinfunction and PINCTRL_PINFUNCTION() macro:
 - Introduce struct pinfunction and PINCTRL_PINFUNCTION() macro

jasperlake:
 -  Replace JSL_COMMUNITY() by INTEL_COMMUNITY_GPPS()

lakefield:
 -  Replace LKF_COMMUNITY() by INTEL_COMMUNITY_GPPS()

lewisburg:
 -  Replace LBG_COMMUNITY() by INTEL_COMMUNITY_SIZE()

lynxpoint:
 -  Convert to use new memeber in struct intel_function

merrifield:
 -  Convert to use new memeber in struct intel_function

meteorlake:
 -  Replace MTL_COMMUNITY() by INTEL_COMMUNITY_GPPS()

moorefield:
 -  Convert to use new memeber in struct intel_function

sunrisepoint:
 -  Replace SPT_COMMUNITY() by INTEL_COMMUNITY_*()

tigerlake:
 -  Replace TGL_COMMUNITY() by INTEL_COMMUNITY_GPPS()
This commit is contained in:
Linus Walleij 2023-01-30 23:46:29 +01:00
commit 5ab4909d0b
24 changed files with 466 additions and 596 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

498
Documentation/driver-api/pin-control.rst
View File

File diff suppressed because it is too large Load Diff

18
drivers/pinctrl/intel/pinctrl-alderlake.c
View File

@ -34,25 +34,11 @@
.gpio_base = (g), \
}
#define ADL_COMMUNITY(b, s, e, g, v) \
{ \
.barno = (b), \
.padown_offset = ADL_##v##_PAD_OWN, \
.padcfglock_offset = ADL_##v##_PADCFGLOCK, \
.hostown_offset = ADL_##v##_HOSTSW_OWN, \
.is_offset = ADL_##v##_GPI_IS, \
.ie_offset = ADL_##v##_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
#define ADL_N_COMMUNITY(b, s, e, g) \
ADL_COMMUNITY(b, s, e, g, N)
INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N)
#define ADL_S_COMMUNITY(b, s, e, g) \
ADL_COMMUNITY(b, s, e, g, S)
INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_S)
/* Alder Lake-N */
static const struct pinctrl_pin_desc adln_pins[] = {

10
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -637,18 +637,18 @@ static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
return vg->soc->functions[selector].name;
return vg->soc->functions[selector].func.name;
}
static int byt_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int *num_groups)
unsigned int *ngroups)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
*groups = vg->soc->functions[selector].groups;
*num_groups = vg->soc->functions[selector].ngroups;
*groups = vg->soc->functions[selector].func.groups;
*ngroups = vg->soc->functions[selector].func.ngroups;
return 0;
}
@ -722,7 +722,7 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
if (group.modes)
byt_set_group_mixed_mux(vg, group, group.modes);
else if (!strcmp(func.name, "gpio"))
else if (!strcmp(func.func.name, "gpio"))
byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
else
byt_set_group_simple_mux(vg, group, group.mode);

31
drivers/pinctrl/intel/pinctrl-broxton.c
View File

@ -20,17 +20,8 @@
#define BXT_GPI_IS 0x100
#define BXT_GPI_IE 0x110
#define BXT_COMMUNITY(s, e) \
{ \
.padown_offset = BXT_PAD_OWN, \
.padcfglock_offset = BXT_PADCFGLOCK, \
.hostown_offset = BXT_HOSTSW_OWN, \
.is_offset = BXT_GPI_IS, \
.ie_offset = BXT_GPI_IE, \
.gpp_size = 32, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
}
#define BXT_COMMUNITY(b, s, e) \
INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, BXT)
/* BXT */
static const struct pinctrl_pin_desc bxt_north_pins[] = {
@ -172,7 +163,7 @@ static const struct intel_function bxt_north_functions[] = {
};
static const struct intel_community bxt_north_communities[] = {
BXT_COMMUNITY(0, 82),
BXT_COMMUNITY(0, 0, 82),
};
static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
@ -289,7 +280,7 @@ static const struct intel_function bxt_northwest_functions[] = {
};
static const struct intel_community bxt_northwest_communities[] = {
BXT_COMMUNITY(0, 71),
BXT_COMMUNITY(0, 0, 71),
};
static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
@ -396,7 +387,7 @@ static const struct intel_function bxt_west_functions[] = {
};
static const struct intel_community bxt_west_communities[] = {
BXT_COMMUNITY(0, 41),
BXT_COMMUNITY(0, 0, 41),
};
static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
@ -472,7 +463,7 @@ static const struct intel_function bxt_southwest_functions[] = {
};
static const struct intel_community bxt_southwest_communities[] = {
BXT_COMMUNITY(0, 30),
BXT_COMMUNITY(0, 0, 30),
};
static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
@ -511,7 +502,7 @@ static const struct pinctrl_pin_desc bxt_south_pins[] = {
};
static const struct intel_community bxt_south_communities[] = {
BXT_COMMUNITY(0, 19),
BXT_COMMUNITY(0, 0, 19),
};
static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
@ -650,7 +641,7 @@ static const struct intel_function apl_north_functions[] = {
};
static const struct intel_community apl_north_communities[] = {
BXT_COMMUNITY(0, 77),
BXT_COMMUNITY(0, 0, 77),
};
static const struct intel_pinctrl_soc_data apl_north_soc_data = {
@ -770,7 +761,7 @@ static const struct intel_function apl_northwest_functions[] = {
};
static const struct intel_community apl_northwest_communities[] = {
BXT_COMMUNITY(0, 76),
BXT_COMMUNITY(0, 0, 76),
};
static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
@ -880,7 +871,7 @@ static const struct intel_function apl_west_functions[] = {
};
static const struct intel_community apl_west_communities[] = {
BXT_COMMUNITY(0, 46),
BXT_COMMUNITY(0, 0, 46),
};
static const struct intel_pinctrl_soc_data apl_west_soc_data = {
@ -972,7 +963,7 @@ static const struct intel_function apl_southwest_functions[] = {
};
static const struct intel_community apl_southwest_communities[] = {
BXT_COMMUNITY(0, 42),
BXT_COMMUNITY(0, 0, 42),
};
static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {

31
drivers/pinctrl/intel/pinctrl-cannonlake.c
View File

@ -15,12 +15,17 @@
#include "pinctrl-intel.h"
#define CNL_PAD_OWN 0x020
#define CNL_PADCFGLOCK 0x080
#define CNL_LP_PAD_OWN 0x020
#define CNL_LP_PADCFGLOCK 0x080
#define CNL_LP_HOSTSW_OWN 0x0b0
#define CNL_LP_GPI_IS 0x100
#define CNL_LP_GPI_IE 0x120
#define CNL_H_PAD_OWN 0x020
#define CNL_H_PADCFGLOCK 0x080
#define CNL_H_HOSTSW_OWN 0x0c0
#define CNL_GPI_IS 0x100
#define CNL_GPI_IE 0x120
#define CNL_H_GPI_IS 0x100
#define CNL_H_GPI_IE 0x120
#define CNL_GPP(r, s, e, g) \
{ \
@ -30,25 +35,11 @@
.gpio_base = (g), \
}
#define CNL_COMMUNITY(b, s, e, g, v) \
{ \
.barno = (b), \
.padown_offset = CNL_PAD_OWN, \
.padcfglock_offset = CNL_PADCFGLOCK, \
.hostown_offset = CNL_##v##_HOSTSW_OWN, \
.is_offset = CNL_GPI_IS, \
.ie_offset = CNL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
#define CNL_LP_COMMUNITY(b, s, e, g) \
CNL_COMMUNITY(b, s, e, g, LP)
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
#define CNL_H_COMMUNITY(b, s, e, g) \
CNL_COMMUNITY(b, s, e, g, H)
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_H)
/* Cannon Lake-H */
static const struct pinctrl_pin_desc cnlh_pins[] = {

13
drivers/pinctrl/intel/pinctrl-cedarfork.c
View File

@ -28,18 +28,7 @@
}
#define CDF_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = CDF_PAD_OWN, \
.padcfglock_offset = CDF_PADCFGLOCK, \
.hostown_offset = CDF_HOSTSW_OWN, \
.is_offset = CDF_GPI_IS, \
.ie_offset = CDF_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
INTEL_COMMUNITY_GPPS(b, s, e, g, CDF)
/* Cedar Fork PCH */
static const struct pinctrl_pin_desc cdf_pins[] = {

6
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -694,7 +694,7 @@ static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->functions[function].name;
return pctrl->soc->functions[function].func.name;
}
static int chv_get_function_groups(struct pinctrl_dev *pctldev,
@ -704,8 +704,8 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->soc->functions[function].groups;
*ngroups = pctrl->soc->functions[function].ngroups;
*groups = pctrl->soc->functions[function].func.groups;
*ngroups = pctrl->soc->functions[function].func.ngroups;
return 0;
}

13
drivers/pinctrl/intel/pinctrl-denverton.c
View File

@ -28,18 +28,7 @@
}
#define DNV_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = DNV_PAD_OWN, \
.padcfglock_offset = DNV_PADCFGLOCK, \
.hostown_offset = DNV_HOSTSW_OWN, \
.is_offset = DNV_GPI_IS, \
.ie_offset = DNV_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
INTEL_COMMUNITY_GPPS(b, s, e, g, DNV)
/* Denverton */
static const struct pinctrl_pin_desc dnv_pins[] = {

24
drivers/pinctrl/intel/pinctrl-elkhartlake.c
View File

@ -27,18 +27,8 @@
.size = ((e) - (s) + 1), \
}
#define EHL_COMMUNITY(s, e, g) \
{ \
.padown_offset = EHL_PAD_OWN, \
.padcfglock_offset = EHL_PADCFGLOCK, \
.hostown_offset = EHL_HOSTSW_OWN, \
.is_offset = EHL_GPI_IS, \
.ie_offset = EHL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
#define EHL_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, EHL)
/* Elkhart Lake */
static const struct pinctrl_pin_desc ehl_community0_pins[] = {
@ -121,7 +111,7 @@ static const struct intel_padgroup ehl_community0_gpps[] = {
};
static const struct intel_community ehl_community0[] = {
EHL_COMMUNITY(0, 66, ehl_community0_gpps),
EHL_COMMUNITY(0, 0, 66, ehl_community0_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community0_soc_data = {
@ -262,7 +252,7 @@ static const struct intel_padgroup ehl_community1_gpps[] = {
};
static const struct intel_community ehl_community1[] = {
EHL_COMMUNITY(0, 112, ehl_community1_gpps),
EHL_COMMUNITY(0, 0, 112, ehl_community1_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {
@ -335,7 +325,7 @@ static const struct intel_padgroup ehl_community3_gpps[] = {
};
static const struct intel_community ehl_community3[] = {
EHL_COMMUNITY(0, 46, ehl_community3_gpps),
EHL_COMMUNITY(0, 0, 46, ehl_community3_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community3_soc_data = {
@ -441,7 +431,7 @@ static const struct intel_padgroup ehl_community4_gpps[] = {
};
static const struct intel_community ehl_community4[] = {
EHL_COMMUNITY(0, 79, ehl_community4_gpps),
EHL_COMMUNITY(0, 0, 79, ehl_community4_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community4_soc_data = {
@ -469,7 +459,7 @@ static const struct intel_padgroup ehl_community5_gpps[] = {
};
static const struct intel_community ehl_community5[] = {
EHL_COMMUNITY(0, 7, ehl_community5_gpps),
EHL_COMMUNITY(0, 0, 7, ehl_community5_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {

13
drivers/pinctrl/intel/pinctrl-emmitsburg.c
View File

@ -28,18 +28,7 @@
}
#define EBG_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = EBG_PAD_OWN, \
.padcfglock_offset = EBG_PADCFGLOCK, \
.hostown_offset = EBG_HOSTSW_OWN, \
.is_offset = EBG_GPI_IS, \
.ie_offset = EBG_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
INTEL_COMMUNITY_GPPS(b, s, e, g, EBG)
/* Emmitsburg */
static const struct pinctrl_pin_desc ebg_pins[] = {

21
drivers/pinctrl/intel/pinctrl-geminilake.c
View File

@ -20,17 +20,8 @@
#define GLK_GPI_IS 0x100
#define GLK_GPI_IE 0x110
#define GLK_COMMUNITY(s, e) \
{ \
.padown_offset = GLK_PAD_OWN, \
.padcfglock_offset = GLK_PADCFGLOCK, \
.hostown_offset = GLK_HOSTSW_OWN, \
.is_offset = GLK_GPI_IS, \
.ie_offset = GLK_GPI_IE, \
.gpp_size = 32, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
}
#define GLK_COMMUNITY(b, s, e) \
INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, GLK)
/* GLK */
static const struct pinctrl_pin_desc glk_northwest_pins[] = {
@ -173,7 +164,7 @@ static const struct intel_function glk_northwest_functions[] = {
};
static const struct intel_community glk_northwest_communities[] = {
GLK_COMMUNITY(0, 79),
GLK_COMMUNITY(0, 0, 79),
};
static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {
@ -306,7 +297,7 @@ static const struct intel_function glk_north_functions[] = {
};
static const struct intel_community glk_north_communities[] = {
GLK_COMMUNITY(0, 79),
GLK_COMMUNITY(0, 0, 79),
};
static const struct intel_pinctrl_soc_data glk_north_soc_data = {
@ -345,7 +336,7 @@ static const struct pinctrl_pin_desc glk_audio_pins[] = {
};
static const struct intel_community glk_audio_communities[] = {
GLK_COMMUNITY(0, 19),
GLK_COMMUNITY(0, 0, 19),
};
static const struct intel_pinctrl_soc_data glk_audio_soc_data = {
@ -427,7 +418,7 @@ static const struct intel_function glk_scc_functions[] = {
};
static const struct intel_community glk_scc_communities[] = {
GLK_COMMUNITY(0, 34),
GLK_COMMUNITY(0, 0, 34),
};
static const struct intel_pinctrl_soc_data glk_scc_soc_data = {

35
drivers/pinctrl/intel/pinctrl-icelake.c
View File

@ -15,12 +15,17 @@
#include "pinctrl-intel.h"
#define ICL_PAD_OWN 0x020
#define ICL_PADCFGLOCK 0x080
#define ICL_HOSTSW_OWN 0x0b0
#define ICL_GPI_IS 0x100
#define ICL_LP_GPI_IE 0x110
#define ICL_N_GPI_IE 0x120
#define ICL_LP_PAD_OWN 0x020
#define ICL_LP_PADCFGLOCK 0x080
#define ICL_LP_HOSTSW_OWN 0x0b0
#define ICL_LP_GPI_IS 0x100
#define ICL_LP_GPI_IE 0x110
#define ICL_N_PAD_OWN 0x020
#define ICL_N_PADCFGLOCK 0x080
#define ICL_N_HOSTSW_OWN 0x0b0
#define ICL_N_GPI_IS 0x100
#define ICL_N_GPI_IE 0x120
#define ICL_GPP(r, s, e, g) \
{ \
@ -30,25 +35,11 @@
.gpio_base = (g), \
}
#define ICL_COMMUNITY(b, s, e, g, v) \
{ \
.barno = (b), \
.padown_offset = ICL_PAD_OWN, \
.padcfglock_offset = ICL_PADCFGLOCK, \
.hostown_offset = ICL_HOSTSW_OWN, \
.is_offset = ICL_GPI_IS, \
.ie_offset = ICL_##v##_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
#define ICL_LP_COMMUNITY(b, s, e, g) \
ICL_COMMUNITY(b, s, e, g, LP)
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP)
#define ICL_N_COMMUNITY(b, s, e, g) \
ICL_COMMUNITY(b, s, e, g, N)
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_N)
/* Ice Lake-LP */
static const struct pinctrl_pin_desc icllp_pins[] = {

126
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -81,13 +81,16 @@
#define PADCFG1_TERM_MASK GENMASK(12, 10)
#define PADCFG1_TERM_20K BIT(2)
#define PADCFG1_TERM_5K BIT(1)
#define PADCFG1_TERM_4K (BIT(2) | BIT(1))
#define PADCFG1_TERM_1K BIT(0)
#define PADCFG1_TERM_952 (BIT(2) | BIT(0))
#define PADCFG1_TERM_833 (BIT(1) | BIT(0))
#define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0))
#define PADCFG2 0x008
#define PADCFG2_DEBEN BIT(0)
#define PADCFG2_DEBOUNCE_SHIFT 1
#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
#define PADCFG2_DEBEN BIT(0)
#define DEBOUNCE_PERIOD_NSEC 31250
@ -369,7 +372,7 @@ static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->functions[function].name;
return pctrl->soc->functions[function].func.name;
}
static int intel_get_function_groups(struct pinctrl_dev *pctldev,
@ -379,8 +382,8 @@ static int intel_get_function_groups(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->soc->functions[function].groups;
*ngroups = pctrl->soc->functions[function].ngroups;
*groups = pctrl->soc->functions[function].func.groups;
*ngroups = pctrl->soc->functions[function].func.ngroups;
return 0;
}
@ -574,6 +577,9 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
case PADCFG1_TERM_1K:
*arg = 1000;
break;
case PADCFG1_TERM_4K:
*arg = 4000;
break;
case PADCFG1_TERM_5K:
*arg = 5000;
break;
@ -599,6 +605,9 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
return -EINVAL;
*arg = 1000;
break;
case PADCFG1_TERM_4K:
*arg = 4000;
break;
case PADCFG1_TERM_5K:
*arg = 5000;
break;
@ -691,21 +700,17 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
raw_spin_lock_irqsave(&pctrl->lock, flags);
value = readl(padcfg1);
value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
/* Set default strength value in case none is given */
if (arg == 1)
arg = 5000;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
break;
case PIN_CONFIG_BIAS_PULL_UP:
value &= ~PADCFG1_TERM_MASK;
value |= PADCFG1_TERM_UP;
/* Set default strength value in case none is given */
if (arg == 1)
arg = 5000;
switch (arg) {
case 20000:
value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
@ -713,6 +718,9 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
case 5000:
value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
break;
case 4000:
value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT;
break;
case 1000:
value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
break;
@ -721,42 +729,46 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
break;
default:
ret = -EINVAL;
break;
}
value |= PADCFG1_TERM_UP;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
switch (arg) {
case 20000:
value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
break;
case 5000:
value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
break;
case 4000:
value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT;
break;
case 1000:
if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
ret = -EINVAL;
break;
}
value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
break;
case 833:
if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
ret = -EINVAL;
break;
}
value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
break;
default:
ret = -EINVAL;
break;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
/* Set default strength value in case none is given */
if (arg == 1)
arg = 5000;
switch (arg) {
case 20000:
value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
break;
case 5000:
value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
break;
case 1000:
if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
ret = -EINVAL;
break;
}
value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
break;
case 833:
if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
ret = -EINVAL;
break;
}
value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
break;
default:
ret = -EINVAL;
}
default:
ret = -EINVAL;
break;
}
@ -1215,13 +1227,8 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
/* Only interrupts that are enabled */
pending &= enabled;
for_each_set_bit(gpp_offset, &pending, padgrp->size) {
unsigned int irq;
irq = irq_find_mapping(gc->irq.domain,
padgrp->gpio_base + gpp_offset);
generic_handle_irq(irq);
}
for_each_set_bit(gpp_offset, &pending, padgrp->size)
generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset);
ret += pending ? 1 : 0;
}
@ -1399,7 +1406,7 @@ static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
for (i = 0; i < ngpps; i++) {
gpps[i] = community->gpps[i];
if (gpps[i].size > 32)
if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE)
return -EINVAL;
/* Special treatment for GPIO base */
@ -1417,7 +1424,7 @@ static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
}
gpps[i].padown_num = padown_num;
padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE);
}
community->gpps = gpps;
@ -1433,7 +1440,7 @@ static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
unsigned int padown_num = 0;
size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
if (community->gpp_size > 32)
if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE)
return -EINVAL;
gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
@ -1451,14 +1458,7 @@ static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
gpps[i].gpio_base = gpps[i].base;
gpps[i].padown_num = padown_num;
/*
* In older hardware the number of padown registers per
* group is fixed regardless of the group size.
*/
if (community->gpp_num_padown_regs)
padown_num += community->gpp_num_padown_regs;
else
padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
padown_num += community->gpp_num_padown_regs;
}
community->ngpps = ngpps;

55
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -36,21 +36,19 @@ struct intel_pingroup {
/**
* struct intel_function - Description about a function
* @name: Name of the function
* @groups: An array of groups for this function
* @ngroups: Number of groups in @groups
* @func: Generic data of the pin function (name and groups of pins)
*/
struct intel_function {
const char *name;
const char * const *groups;
size_t ngroups;
struct pinfunction func;
};
#define INTEL_PINCTRL_MAX_GPP_SIZE 32
/**
* struct intel_padgroup - Hardware pad group information
* @reg_num: GPI_IS register number
* @base: Starting pin of this group
* @size: Size of this group (maximum is 32).
* @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE).
* @gpio_base: Starting GPIO base of this group
* @padown_num: PAD_OWN register number (assigned by the core driver)
*
@ -96,8 +94,7 @@ enum {
* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
* HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
* @gpp_num_padown_regs: Number of pad registers each pad group consumes at
* minimum. Use %0 if the number of registers can be
* determined by the size of the group.
* minimum. Used when @gpps is %NULL.
* @gpps: Pad groups if the controller has variable size pad groups
* @ngpps: Number of pad groups in this community
* @pad_map: Optional non-linear mapping of the pads
@ -106,11 +103,13 @@ enum {
* @regs: Community specific common registers (reserved for core driver)
* @pad_regs: Community specific pad registers (reserved for core driver)
*
* In some of Intel GPIO host controllers this driver supports each pad group
* In older Intel GPIO host controllers, this driver supports, each pad group
* is of equal size (except the last one). In that case the driver can just
* fill in @gpp_size field and let the core driver to handle the rest. If
* the controller has pad groups of variable size the client driver can
* pass custom @gpps and @ngpps instead.
* fill in @gpp_size and @gpp_num_padown_regs fields and let the core driver
* to handle the rest.
*
* In newer Intel GPIO host controllers each pad group is of variable size,
* so the client driver can pass custom @gpps and @ngpps instead.
*/
struct intel_community {
unsigned int barno;
@ -143,6 +142,28 @@ struct intel_community {
#define PINCTRL_FEATURE_BLINK BIT(4)
#define PINCTRL_FEATURE_EXP BIT(5)
#define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \
{ \
.barno = (b), \
.padown_offset = soc ## _PAD_OWN, \
.padcfglock_offset = soc ## _PADCFGLOCK, \
.hostown_offset = soc ## _HOSTSW_OWN, \
.is_offset = soc ## _GPI_IS, \
.ie_offset = soc ## _GPI_IE, \
.gpp_size = (gs), \
.gpp_num_padown_regs = (gn), \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = (n), \
}
#define INTEL_COMMUNITY_GPPS(b, s, e, g, soc) \
__INTEL_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), 0, 0, soc)
#define INTEL_COMMUNITY_SIZE(b, s, e, gs, gn, soc) \
__INTEL_COMMUNITY(b, s, e, NULL, 0, gs, gn, soc)
/**
* PIN_GROUP - Declare a pin group
* @n: Name of the group
@ -158,11 +179,9 @@ struct intel_community {
.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \
}
#define FUNCTION(n, g) \
{ \
.name = (n), \
.groups = (g), \
.ngroups = ARRAY_SIZE((g)), \
#define FUNCTION(n, g) \
{ \
.func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \
}
/**

13
drivers/pinctrl/intel/pinctrl-jasperlake.c
View File

@ -29,18 +29,7 @@
}
#define JSL_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = JSL_PAD_OWN, \
.padcfglock_offset = JSL_PADCFGLOCK, \
.hostown_offset = JSL_HOSTSW_OWN, \
.is_offset = JSL_GPI_IS, \
.ie_offset = JSL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
INTEL_COMMUNITY_GPPS(b, s, e, g, JSL)
/* Jasper Lake */
static const struct pinctrl_pin_desc jsl_pins[] = {

13
drivers/pinctrl/intel/pinctrl-lakefield.c
View File

@ -29,18 +29,7 @@
}
#define LKF_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = LKF_PAD_OWN, \
.padcfglock_offset = LKF_PADCFGLOCK, \
.hostown_offset = LKF_HOSTSW_OWN, \
.is_offset = LKF_GPI_IS, \
.ie_offset = LKF_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
INTEL_COMMUNITY_GPPS(b, s, e, g, LKF)
/* Lakefield */
static const struct pinctrl_pin_desc lkf_pins[] = {

12
drivers/pinctrl/intel/pinctrl-lewisburg.c
View File

@ -21,17 +21,7 @@
#define LBG_GPI_IE 0x110
#define LBG_COMMUNITY(b, s, e) \
{ \
.barno = (b), \
.padown_offset = LBG_PAD_OWN, \
.padcfglock_offset = LBG_PADCFGLOCK, \
.hostown_offset = LBG_HOSTSW_OWN, \
.is_offset = LBG_GPI_IS, \
.ie_offset = LBG_GPI_IE, \
.gpp_size = 24, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
}
INTEL_COMMUNITY_SIZE(b, s, e, 24, 3, LBG)
/* Lewisburg */
static const struct pinctrl_pin_desc lbg_pins[] = {

8
drivers/pinctrl/intel/pinctrl-lynxpoint.c
View File

@ -341,18 +341,18 @@ static const char *lp_get_function_name(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
return lg->soc->functions[selector].name;
return lg->soc->functions[selector].func.name;
}
static int lp_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int *num_groups)
unsigned int *ngroups)
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
*groups = lg->soc->functions[selector].groups;
*num_groups = lg->soc->functions[selector].ngroups;
*groups = lg->soc->functions[selector].func.groups;
*ngroups = lg->soc->functions[selector].func.ngroups;
return 0;
}

6
drivers/pinctrl/intel/pinctrl-merrifield.c
View File

@ -576,7 +576,7 @@ static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
{
struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
return mp->functions[function].name;
return mp->functions[function].func.name;
}
static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
@ -586,8 +586,8 @@ static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
{
struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
*groups = mp->functions[function].groups;
*ngroups = mp->functions[function].ngroups;
*groups = mp->functions[function].func.groups;
*ngroups = mp->functions[function].func.ngroups;
return 0;
}

23
drivers/pinctrl/intel/pinctrl-meteorlake.c
View File

@ -14,11 +14,11 @@
#include "pinctrl-intel.h"
#define MTL_PAD_OWN 0x0b0
#define MTL_PADCFGLOCK 0x110
#define MTL_HOSTSW_OWN 0x140
#define MTL_GPI_IS 0x200
#define MTL_GPI_IE 0x210
#define MTL_P_PAD_OWN 0x0b0
#define MTL_P_PADCFGLOCK 0x110
#define MTL_P_HOSTSW_OWN 0x140
#define MTL_P_GPI_IS 0x200
#define MTL_P_GPI_IE 0x210
#define MTL_GPP(r, s, e, g) \
{ \
@ -29,18 +29,7 @@
}
#define MTL_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = MTL_PAD_OWN, \
.padcfglock_offset = MTL_PADCFGLOCK, \
.hostown_offset = MTL_HOSTSW_OWN, \
.is_offset = MTL_GPI_IS, \
.ie_offset = MTL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P)
/* Meteor Lake-P */
static const struct pinctrl_pin_desc mtlp_pins[] = {

6
drivers/pinctrl/intel/pinctrl-moorefield.c
View File

@ -530,7 +530,7 @@ static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned
{
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
return mp->functions[function].name;
return mp->functions[function].func.name;
}
static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
@ -538,8 +538,8 @@ static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int f
{
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
*groups = mp->functions[function].groups;
*ngroups = mp->functions[function].ngroups;
*groups = mp->functions[function].func.groups;
*ngroups = mp->functions[function].func.ngroups;
return 0;
}

37
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@ -15,31 +15,17 @@
#include "pinctrl-intel.h"
#define SPT_PAD_OWN 0x020
#define SPT_H_PAD_OWN 0x020
#define SPT_H_PADCFGLOCK 0x090
#define SPT_H_HOSTSW_OWN 0x0d0
#define SPT_H_GPI_IS 0x100
#define SPT_H_GPI_IE 0x120
#define SPT_LP_PAD_OWN 0x020
#define SPT_LP_PADCFGLOCK 0x0a0
#define SPT_HOSTSW_OWN 0x0d0
#define SPT_GPI_IS 0x100
#define SPT_GPI_IE 0x120
#define SPT_COMMUNITY(b, s, e, g, n, v, gs, gn) \
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_##v##_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \
.gpp_size = (gs), \
.gpp_num_padown_regs = (gn), \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = (n), \
}
#define SPT_LP_COMMUNITY(b, s, e) \
SPT_COMMUNITY(b, s, e, NULL, 0, LP, 24, 4)
#define SPT_LP_HOSTSW_OWN 0x0d0
#define SPT_LP_GPI_IS 0x100
#define SPT_LP_GPI_IE 0x120
#define SPT_H_GPP(r, s, e, g) \
{ \
@ -50,7 +36,10 @@
}
#define SPT_H_COMMUNITY(b, s, e, g) \
SPT_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), H, 0, 0)
INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H)
#define SPT_LP_COMMUNITY(b, s, e) \
INTEL_COMMUNITY_SIZE(b, s, e, 24, 4, SPT_LP)
/* Sunrisepoint-LP */
static const struct pinctrl_pin_desc sptlp_pins[] = {

30
drivers/pinctrl/intel/pinctrl-tigerlake.c
View File

@ -15,13 +15,17 @@
#include "pinctrl-intel.h"
#define TGL_PAD_OWN 0x020
#define TGL_LP_PAD_OWN 0x020
#define TGL_LP_PADCFGLOCK 0x080
#define TGL_H_PADCFGLOCK 0x090
#define TGL_LP_HOSTSW_OWN 0x0b0
#define TGL_LP_GPI_IS 0x100
#define TGL_LP_GPI_IE 0x120
#define TGL_H_PAD_OWN 0x020
#define TGL_H_PADCFGLOCK 0x090
#define TGL_H_HOSTSW_OWN 0x0c0
#define TGL_GPI_IS 0x100
#define TGL_GPI_IE 0x120
#define TGL_H_GPI_IS 0x100
#define TGL_H_GPI_IE 0x120
#define TGL_GPP(r, s, e, g) \
{ \
@ -31,25 +35,11 @@
.gpio_base = (g), \
}
#define TGL_COMMUNITY(b, s, e, g, v) \
{ \
.barno = (b), \
.padown_offset = TGL_PAD_OWN, \
.padcfglock_offset = TGL_##v##_PADCFGLOCK, \
.hostown_offset = TGL_##v##_HOSTSW_OWN, \
.is_offset = TGL_GPI_IS, \
.ie_offset = TGL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
#define TGL_LP_COMMUNITY(b, s, e, g) \
TGL_COMMUNITY(b, s, e, g, LP)
INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP)
#define TGL_H_COMMUNITY(b, s, e, g) \
TGL_COMMUNITY(b, s, e, g, H)
INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_H)
/* Tiger Lake-LP */
static const struct pinctrl_pin_desc tgllp_pins[] = {

20
include/linux/pinctrl/pinctrl.h
View File

@ -206,6 +206,26 @@ extern int pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
const char *pin_group, const unsigned **pins,
unsigned *num_pins);
/**
* struct pinfunction - Description about a function
* @name: Name of the function
* @groups: An array of groups for this function
* @ngroups: Number of groups in @groups
*/
struct pinfunction {
const char *name;
const char * const *groups;
size_t ngroups;
};
/* Convenience macro to define a single named pinfunction */
#define PINCTRL_PINFUNCTION(_name, _groups, _ngroups) \
(struct pinfunction) { \
.name = (_name), \
.groups = (_groups), \
.ngroups = (_ngroups), \
}
#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PINCTRL)
extern struct pinctrl_dev *of_pinctrl_get(struct device_node *np);
#else