pwm: sun4i: Add an optional probe for bus clock
H6 PWM core needs bus clock to be enabled in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Clément Péron <peron.clem@gmail.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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@ -78,6 +78,7 @@ struct sun4i_pwm_data {
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struct sun4i_pwm_chip {
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struct pwm_chip chip;
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struct clk *bus_clk;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *base;
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@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
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}
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}
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pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
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if (IS_ERR(pwm->bus_clk)) {
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if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "get bus clock failed %pe\n",
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pwm->bus_clk);
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return PTR_ERR(pwm->bus_clk);
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}
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pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
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if (IS_ERR(pwm->rst)) {
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if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
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@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
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return ret;
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}
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/*
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* We're keeping the bus clock on for the sake of simplicity.
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* Actually it only needs to be on for hardware register accesses.
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*/
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ret = clk_prepare_enable(pwm->bus_clk);
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if (ret) {
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dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
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ERR_PTR(ret));
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goto err_bus;
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}
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &sun4i_pwm_ops;
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pwm->chip.base = -1;
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@ -427,6 +447,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
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return 0;
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err_pwm_add:
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clk_disable_unprepare(pwm->bus_clk);
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err_bus:
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reset_control_assert(pwm->rst);
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return ret;
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@ -441,6 +463,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
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if (ret)
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return ret;
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clk_disable_unprepare(pwm->bus_clk);
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reset_control_assert(pwm->rst);
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return 0;
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