intel-pinctrl for v5.10-1
* Add last part of cleanup Cherryview driver to align with other drivers * Due to above clean up Cherryview and Baytrail drivers to use common API The following is an automated git shortlog grouped by driver: baytrail: - Switch to use intel_pinctrl_get_soc_data() cherryview: - Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs - Switch to use intel_pinctrl_get_soc_data() - Utilize temporary variable to hold device pointer - Switch to use struct intel_pinctrl - Move custom community members to separate data struct - Drop stale comment intel: - Update header block to reflect direct dependencies - Extract intel_pinctrl_get_soc_data() helper for wider use -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAl9kyM0ACgkQb7wzTHR8 rCg6+BAAp+nlCJ5UlfrzjuH3+5zEegnGgck2bq9dlSRgapCXjq1fww6/9UZVvF9Q 1smQcs5bRnwk/HH0eG0pRHPNQGaExAYP5RaKAPmhZ1g/DaT9NN607gi49fgAq24l SygiIUiQ5ObSnTw0h33sHII2vKRqpBfwTqWAnJ8yvAThGSqQUPr7QUP0zpghZ2h1 EN9FK2UX042DiKdK2H6w+D0qN1J/frbogMdqumplkIASw57CCKz2hf/bg3AklNdQ yjloAj/bvHC6yOp87B/anokMHphLnUWXpZR1NtLePL67JRCEp0TT+OOoehYJ1/FC 3boIPr4ihAxdCGFdo3tcxLlVgphYuwdMCjqv4w18UY1hBW9yjs5zPd5jdXT6tOR3 f7z7+TyWbRAOQawbSpNLgrrv5o1KTkVW8sG9qOH1bL9QHR2kin8rghH9ATlO6rIy yj7TkYIdmDCAvFYHw5NHng6D/9dyCCwAF3pBYxJwMevlo3y0OPdyYRobXqmgnitl rnOO2OSHIt45EqlibJCaQNr2fX19IogNzkoN1FI3P5uVSjsRuB8ljuQ1IEJXSH05 Y24k16YX13mWBPuT8E8Iw0UbLBZsBE1hzsrUpnYOE9BRb6XKSUuzKbdKurE+CCBC 4nu1Caof71wW8en57mFEFEgcm1tJHumySq3J+tPsyh61wfAZJ/M= =H2KZ -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.10-1 * Add last part of cleanup Cherryview driver to align with other drivers * Due to above clean up Cherryview and Baytrail drivers to use common API The following is an automated git shortlog grouped by driver: baytrail: - Switch to use intel_pinctrl_get_soc_data() cherryview: - Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs - Switch to use intel_pinctrl_get_soc_data() - Utilize temporary variable to hold device pointer - Switch to use struct intel_pinctrl - Move custom community members to separate data struct - Drop stale comment intel: - Update header block to reflect direct dependencies - Extract intel_pinctrl_get_soc_data() helper for wider use
This commit is contained in:
Linus Walleij
commit
5b398f8fc1
@ -6,11 +6,7 @@ if (X86 || COMPILE_TEST)
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config PINCTRL_BAYTRAIL
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bool "Intel Baytrail GPIO pin control"
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depends on ACPI
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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select PINCTRL_INTEL
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help
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driver for memory mapped GPIO functionality on Intel Baytrail
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platforms. Supports 3 banks with 102, 28 and 44 gpios.
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@ -22,11 +18,7 @@ config PINCTRL_BAYTRAIL
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config PINCTRL_CHERRYVIEW
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tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
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depends on ACPI
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select PINCTRL_INTEL
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help
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Cherryview/Braswell pinctrl driver provides an interface that
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allows configuring of SoC pins and using them as GPIOs.
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@ -1635,28 +1635,14 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = {
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static int byt_pinctrl_probe(struct platform_device *pdev)
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{
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const struct intel_pinctrl_soc_data *soc_data = NULL;
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const struct intel_pinctrl_soc_data **soc_table;
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const struct intel_pinctrl_soc_data *soc_data;
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struct device *dev = &pdev->dev;
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struct acpi_device *acpi_dev;
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struct intel_pinctrl *vg;
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int i, ret;
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int ret;
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acpi_dev = ACPI_COMPANION(dev);
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if (!acpi_dev)
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return -ENODEV;
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soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
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for (i = 0; soc_table[i]; i++) {
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if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
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soc_data = soc_table[i];
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break;
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}
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}
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if (!soc_data)
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return -ENODEV;
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soc_data = intel_pinctrl_get_soc_data(pdev);
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if (IS_ERR(soc_data))
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return PTR_ERR(soc_data);
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vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
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if (!vg)
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@ -58,6 +58,7 @@
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#define CHV_PADCTRL1_CFGLOCK BIT(31)
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#define CHV_PADCTRL1_INVRXTX_SHIFT 4
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#define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4)
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#define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7)
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#define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6)
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#define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5)
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#define CHV_PADCTRL1_ODEN BIT(3)
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@ -73,35 +74,11 @@ struct intel_pad_context {
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};
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/**
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* struct chv_pinctrl - CHV pinctrl private structure
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* @dev: Pointer to the parent device
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* @pctldesc: Pin controller description
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* @pctldev: Pointer to the pin controller device
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* @chip: GPIO chip in this pin controller
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* @irqchip: IRQ chip in this pin controller
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* @soc: Community specific pin configuration data
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* @communities: All communities in this pin controller
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* @ncommunities: Number of communities in this pin controller
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* @context: Configuration saved over system sleep
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* @irq: Our parent irq
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* struct intel_community_context - community context for Cherryview
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* @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
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* @saved_intmask: Interrupt mask saved for system sleep
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*
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* The first group in @groups is expected to contain all pins that can be
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* used as GPIOs.
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*/
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struct chv_pinctrl {
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struct device *dev;
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struct pinctrl_desc pctldesc;
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struct pinctrl_dev *pctldev;
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struct gpio_chip chip;
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struct irq_chip irqchip;
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const struct intel_pinctrl_soc_data *soc;
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struct intel_community *communities;
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size_t ncommunities;
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struct intel_pinctrl_context context;
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int irq;
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struct intel_community_context {
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unsigned int intr_lines[16];
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u32 saved_intmask;
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};
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@ -587,14 +564,14 @@ static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
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*/
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static DEFINE_RAW_SPINLOCK(chv_lock);
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static u32 chv_pctrl_readl(struct chv_pinctrl *pctrl, unsigned int offset)
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static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
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{
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const struct intel_community *community = &pctrl->communities[0];
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return readl(community->regs + offset);
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}
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static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 value)
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static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
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{
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const struct intel_community *community = &pctrl->communities[0];
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void __iomem *reg = community->regs + offset;
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@ -604,7 +581,7 @@ static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32
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readl(reg);
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}
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static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
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static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
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unsigned int reg)
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{
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const struct intel_community *community = &pctrl->communities[0];
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@ -616,12 +593,12 @@ static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
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return community->pad_regs + offset + reg;
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}
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static u32 chv_readl(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset)
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static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
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{
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return readl(chv_padreg(pctrl, pin, offset));
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}
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static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
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static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
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{
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void __iomem *reg = chv_padreg(pctrl, pin, offset);
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@ -631,14 +608,14 @@ static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int
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}
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/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
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static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
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static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
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{
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return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
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}
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static int chv_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->ngroups;
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}
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@ -646,7 +623,7 @@ static int chv_get_groups_count(struct pinctrl_dev *pctldev)
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static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->groups[group].name;
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}
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@ -654,7 +631,7 @@ static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
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static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
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const unsigned int **pins, unsigned int *npins)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*pins = pctrl->soc->groups[group].pins;
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*npins = pctrl->soc->groups[group].npins;
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@ -664,7 +641,7 @@ static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
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static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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unsigned int offset)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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u32 ctrl0, ctrl1;
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bool locked;
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@ -703,7 +680,7 @@ static const struct pinctrl_ops chv_pinctrl_ops = {
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static int chv_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->nfunctions;
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}
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@ -711,7 +688,7 @@ static int chv_get_functions_count(struct pinctrl_dev *pctldev)
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static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
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unsigned int function)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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return pctrl->soc->functions[function].name;
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}
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@ -721,7 +698,7 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev,
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const char * const **groups,
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unsigned int * const ngroups)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctrl->soc->functions[function].groups;
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*ngroups = pctrl->soc->functions[function].ngroups;
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@ -731,7 +708,7 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev,
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static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int function, unsigned int group)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pingroup *grp;
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unsigned long flags;
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int i;
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@ -789,14 +766,25 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
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return 0;
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}
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static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
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static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
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unsigned int offset)
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{
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u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
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u32 value;
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/*
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* One some devices the GPIO should output the inverted value from what
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* device-drivers / ACPI code expects (inverted external buffer?). The
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* BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
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* preserve this flag if the pin is already setup as GPIO.
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*/
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value = chv_readl(pctrl, offset, CHV_PADCTRL0);
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if (value & CHV_PADCTRL0_GPIOEN)
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invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
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value = chv_readl(pctrl, offset, CHV_PADCTRL1);
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value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
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value &= ~CHV_PADCTRL1_INVRXTX_MASK;
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value &= ~invrxtx_mask;
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chv_writel(pctrl, offset, CHV_PADCTRL1, value);
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}
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@ -804,7 +792,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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u32 value;
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@ -818,12 +806,13 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
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return -EBUSY;
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}
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} else {
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struct intel_community_context *cctx = &pctrl->context.communities[0];
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int i;
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/* Reset the interrupt mapping */
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for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
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if (pctrl->intr_lines[i] == offset) {
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pctrl->intr_lines[i] = 0;
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for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
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if (cctx->intr_lines[i] == offset) {
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cctx->intr_lines[i] = 0;
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break;
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}
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}
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@ -857,7 +846,7 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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raw_spin_lock_irqsave(&chv_lock, flags);
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@ -872,7 +861,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset, bool input)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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u32 ctrl0;
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@ -903,7 +892,7 @@ static const struct pinmux_ops chv_pinmux_ops = {
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static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *config)
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{
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struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned long flags;
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u32 ctrl0, ctrl1;
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@ -980,7 +969,7 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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return 0;
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}
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static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
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static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
|
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enum pin_config_param param, u32 arg)
|
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{
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||||
unsigned long flags;
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||||
@ -1045,7 +1034,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
|
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return 0;
|
||||
}
|
||||
|
||||
static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
|
||||
static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
|
||||
bool enable)
|
||||
{
|
||||
unsigned long flags;
|
||||
@ -1068,7 +1057,7 @@ static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
|
||||
static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
unsigned long *configs, unsigned int nconfigs)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
enum pin_config_param param;
|
||||
int i, ret;
|
||||
u32 arg;
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||||
@ -1169,7 +1158,7 @@ static struct pinctrl_desc chv_pinctrl_desc = {
|
||||
|
||||
static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
unsigned long flags;
|
||||
u32 ctrl0, cfg;
|
||||
|
||||
@ -1187,7 +1176,7 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
|
||||
static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
unsigned long flags;
|
||||
u32 ctrl0;
|
||||
|
||||
@ -1207,7 +1196,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
|
||||
static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
u32 ctrl0, direction;
|
||||
unsigned long flags;
|
||||
|
||||
@ -1250,7 +1239,7 @@ static const struct gpio_chip chv_gpio_chip = {
|
||||
static void chv_gpio_irq_ack(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
int pin = irqd_to_hwirq(d);
|
||||
u32 intr_line;
|
||||
|
||||
@ -1267,7 +1256,7 @@ static void chv_gpio_irq_ack(struct irq_data *d)
|
||||
static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
int pin = irqd_to_hwirq(d);
|
||||
u32 value, intr_line;
|
||||
unsigned long flags;
|
||||
@ -1312,7 +1301,8 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
|
||||
*/
|
||||
if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
unsigned int pin = irqd_to_hwirq(d);
|
||||
irq_flow_handler_t handler;
|
||||
unsigned long flags;
|
||||
@ -1329,9 +1319,9 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
|
||||
else
|
||||
handler = handle_edge_irq;
|
||||
|
||||
if (!pctrl->intr_lines[intsel]) {
|
||||
if (!cctx->intr_lines[intsel]) {
|
||||
irq_set_handler_locked(d, handler);
|
||||
pctrl->intr_lines[intsel] = pin;
|
||||
cctx->intr_lines[intsel] = pin;
|
||||
}
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
}
|
||||
@ -1343,7 +1333,8 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
|
||||
static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
unsigned int pin = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
@ -1388,7 +1379,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
value &= CHV_PADCTRL0_INTSEL_MASK;
|
||||
value >>= CHV_PADCTRL0_INTSEL_SHIFT;
|
||||
|
||||
pctrl->intr_lines[value] = pin;
|
||||
cctx->intr_lines[value] = pin;
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
@ -1403,8 +1394,9 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
static void chv_gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
unsigned long pending;
|
||||
unsigned long flags;
|
||||
@ -1419,7 +1411,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
|
||||
for_each_set_bit(intr_line, &pending, community->nirqs) {
|
||||
unsigned int irq, offset;
|
||||
|
||||
offset = pctrl->intr_lines[intr_line];
|
||||
offset = cctx->intr_lines[intr_line];
|
||||
irq = irq_find_mapping(gc->irq.domain, offset);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
@ -1472,7 +1464,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
|
||||
unsigned long *valid_mask,
|
||||
unsigned int ngpios)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
int i;
|
||||
|
||||
@ -1494,7 +1486,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
|
||||
|
||||
static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
|
||||
/*
|
||||
@ -1520,7 +1512,7 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
|
||||
static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
const struct intel_padgroup *gpp;
|
||||
int ret, i;
|
||||
@ -1539,7 +1531,7 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
|
||||
static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
||||
{
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
const struct intel_padgroup *gpp;
|
||||
@ -1605,7 +1597,7 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
|
||||
acpi_physical_address address, u32 bits, u64 *value,
|
||||
void *handler_context, void *region_context)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = region_context;
|
||||
struct intel_pinctrl *pctrl = region_context;
|
||||
unsigned long flags;
|
||||
acpi_status ret = AE_OK;
|
||||
|
||||
@ -1625,34 +1617,23 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
|
||||
|
||||
static int chv_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct intel_pinctrl_soc_data *soc_data = NULL;
|
||||
const struct intel_pinctrl_soc_data **soc_table;
|
||||
const struct intel_pinctrl_soc_data *soc_data;
|
||||
struct intel_community *community;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct chv_pinctrl *pctrl;
|
||||
struct acpi_device *adev;
|
||||
struct acpi_device *adev = ACPI_COMPANION(dev);
|
||||
struct intel_pinctrl *pctrl;
|
||||
acpi_status status;
|
||||
int ret, irq, i;
|
||||
int ret, irq;
|
||||
|
||||
adev = ACPI_COMPANION(&pdev->dev);
|
||||
if (!adev)
|
||||
return -ENODEV;
|
||||
|
||||
soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
|
||||
for (i = 0; soc_table[i]; i++) {
|
||||
if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
|
||||
soc_data = soc_table[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!soc_data)
|
||||
return -ENODEV;
|
||||
soc_data = intel_pinctrl_get_soc_data(pdev);
|
||||
if (IS_ERR(soc_data))
|
||||
return PTR_ERR(soc_data);
|
||||
|
||||
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
|
||||
if (!pctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
pctrl->dev = &pdev->dev;
|
||||
pctrl->dev = dev;
|
||||
pctrl->soc = soc_data;
|
||||
|
||||
pctrl->ncommunities = pctrl->soc->ncommunities;
|
||||
@ -1677,19 +1658,24 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
|
||||
return -ENOMEM;
|
||||
#endif
|
||||
|
||||
pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
|
||||
sizeof(*pctrl->context.communities),
|
||||
GFP_KERNEL);
|
||||
if (!pctrl->context.communities)
|
||||
return -ENOMEM;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
pctrl->pctldesc = chv_pinctrl_desc;
|
||||
pctrl->pctldesc.name = dev_name(&pdev->dev);
|
||||
pctrl->pctldesc.name = dev_name(dev);
|
||||
pctrl->pctldesc.pins = pctrl->soc->pins;
|
||||
pctrl->pctldesc.npins = pctrl->soc->npins;
|
||||
|
||||
pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
|
||||
pctrl);
|
||||
pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
|
||||
if (IS_ERR(pctrl->pctldev)) {
|
||||
dev_err(&pdev->dev, "failed to register pinctrl driver\n");
|
||||
dev_err(dev, "failed to register pinctrl driver\n");
|
||||
return PTR_ERR(pctrl->pctldev);
|
||||
}
|
||||
|
||||
@ -1702,7 +1688,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
|
||||
chv_pinctrl_mmio_access_handler,
|
||||
NULL, pctrl);
|
||||
if (ACPI_FAILURE(status))
|
||||
dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
|
||||
dev_err(dev, "failed to install ACPI addr space handler\n");
|
||||
|
||||
platform_set_drvdata(pdev, pctrl);
|
||||
|
||||
@ -1711,7 +1697,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
|
||||
|
||||
static int chv_pinctrl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
|
||||
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
|
||||
acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
|
||||
@ -1724,13 +1710,14 @@ static int chv_pinctrl_remove(struct platform_device *pdev)
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int chv_pinctrl_suspend_noirq(struct device *dev)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
|
||||
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
raw_spin_lock_irqsave(&chv_lock, flags);
|
||||
|
||||
pctrl->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
|
||||
cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
|
||||
|
||||
for (i = 0; i < pctrl->soc->npins; i++) {
|
||||
const struct pinctrl_pin_desc *desc;
|
||||
@ -1753,7 +1740,8 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
|
||||
|
||||
static int chv_pinctrl_resume_noirq(struct device *dev)
|
||||
{
|
||||
struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
|
||||
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
@ -1797,7 +1785,7 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
|
||||
* the interrupt mask register as well.
|
||||
*/
|
||||
chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
|
||||
chv_pctrl_writel(pctrl, CHV_INTMASK, pctrl->saved_intmask);
|
||||
chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
|
||||
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
|
||||
|
||||
@ -1414,9 +1414,6 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
|
||||
struct intel_pinctrl *pctrl;
|
||||
int i, ret, irq;
|
||||
|
||||
if (!soc_data)
|
||||
return -EINVAL;
|
||||
|
||||
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
|
||||
if (!pctrl)
|
||||
return -ENOMEM;
|
||||
@ -1505,11 +1502,26 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
|
||||
const struct intel_pinctrl_soc_data *data;
|
||||
|
||||
data = device_get_match_data(&pdev->dev);
|
||||
if (!data)
|
||||
return -ENODATA;
|
||||
|
||||
return intel_pinctrl_probe(pdev, data);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
|
||||
|
||||
int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
|
||||
{
|
||||
const struct intel_pinctrl_soc_data *data;
|
||||
|
||||
data = intel_pinctrl_get_soc_data(pdev);
|
||||
if (IS_ERR(data))
|
||||
return PTR_ERR(data);
|
||||
|
||||
return intel_pinctrl_probe(pdev, data);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
|
||||
|
||||
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
|
||||
{
|
||||
const struct intel_pinctrl_soc_data *data = NULL;
|
||||
const struct intel_pinctrl_soc_data **table;
|
||||
@ -1532,15 +1544,15 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
|
||||
|
||||
id = platform_get_device_id(pdev);
|
||||
if (!id)
|
||||
return -ENODEV;
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
table = (const struct intel_pinctrl_soc_data **)id->driver_data;
|
||||
data = table[pdev->id];
|
||||
}
|
||||
|
||||
return intel_pinctrl_probe(pdev, data);
|
||||
return data ?: ERR_PTR(-ENODATA);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
|
||||
EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
|
||||
|
||||
@ -10,12 +10,15 @@
|
||||
#ifndef PINCTRL_INTEL_H
|
||||
#define PINCTRL_INTEL_H
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/compiler_types.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
|
||||
struct pinctrl_pin_desc;
|
||||
struct platform_device;
|
||||
struct device;
|
||||
|
||||
@ -194,6 +197,8 @@ struct intel_pinctrl_soc_data {
|
||||
size_t ncommunities;
|
||||
};
|
||||
|
||||
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
|
||||
|
||||
struct intel_pad_context;
|
||||
struct intel_community_context;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user