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Second Round of Renesas ARM-based SoC DT updates for v3.11

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* Increased DT coverage for renesas-intc-irqpin
   by Guennadi Liakhovetski
 * Clean up of address format used in sh73a0 dtsi file
   by Guennadi Liakhovetski
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Merge tag 'renesas-dt2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

From Simon Horman:

Second Round of Renesas ARM-based SoC DT updates for v3.11

* Increased DT coverage for renesas-intc-irqpin
  by Guennadi Liakhovetski
* Clean up of address format used in sh73a0 dtsi file
  by Guennadi Liakhovetski

* tag 'renesas-dt2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: irqpin: add a DT property to enable masking on parent
  ARM: shmobile: sh73a0: remove "0x" prefix from DT node names
  irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-06-21 15:28:16 +02:00
commit 5b520c94b3
3 changed files with 33 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt Normal file
View File

@ -0,0 +1,16 @@
DT bindings for the R-/SH-Mobile irqpin controller
Required properties:
- compatible: has to be "renesas,intc-irqpin"
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory
Optional properties:
- any properties, listed in interrupts.txt, and any standard resource allocation
properties
- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
if different from the default 4 bits
- control-parent: disable and enable interrupts on the parent interrupt
controller, needed for some broken implementations

18
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -119,7 +119,7 @@
0 32 0x4>;
};
i2c0: i2c@0xe6820000 {
i2c0: i2c@e6820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
@ -131,7 +131,7 @@
0 170 0x4>;
};
i2c1: i2c@0xe6822000 {
i2c1: i2c@e6822000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
@ -143,7 +143,7 @@
0 54 0x4>;
};
i2c2: i2c@0xe6824000 {
i2c2: i2c@e6824000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
@ -155,7 +155,7 @@
0 174 0x4>;
};
i2c3: i2c@0xe6826000 {
i2c3: i2c@e6826000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
@ -167,7 +167,7 @@
0 186 0x4>;
};
i2c4: i2c@0xe6828000 {
i2c4: i2c@e6828000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
@ -179,7 +179,7 @@
0 190 0x4>;
};
mmcif: mmcif@0x10010000 {
mmcif: mmcif@e6bd0000 {
compatible = "renesas,sh-mmcif";
reg = <0xe6bd0000 0x100>;
interrupt-parent = <&gic>;
@ -189,7 +189,7 @@
status = "disabled";
};
sdhi0: sdhi@0xee100000 {
sdhi0: sdhi@ee100000 {
compatible = "renesas,r8a7740-sdhi";
reg = <0xee100000 0x100>;
interrupt-parent = <&gic>;
@ -201,7 +201,7 @@
};
/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
sdhi1: sdhi@0xee120000 {
sdhi1: sdhi@ee120000 {
compatible = "renesas,r8a7740-sdhi";
reg = <0xee120000 0x100>;
interrupt-parent = <&gic>;
@ -212,7 +212,7 @@
status = "disabled";
};
sdhi2: sdhi@0xee140000 {
sdhi2: sdhi@ee140000 {
compatible = "renesas,r8a7740-sdhi";
reg = <0xee140000 0x100>;
interrupt-parent = <&gic>;

9
drivers/irqchip/irq-renesas-intc-irqpin.c
View File

@ -18,6 +18,7 @@
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
@ -347,8 +348,14 @@ static int intc_irqpin_probe(struct platform_device *pdev)
}
/* deal with driver instance configuration */
if (pdata)
if (pdata) {
memcpy(&p->config, pdata, sizeof(*pdata));
} else {
of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
&p->config.sense_bitfield_width);
p->config.control_parent = of_property_read_bool(pdev->dev.of_node,
"control-parent");
}
if (!p->config.sense_bitfield_width)
p->config.sense_bitfield_width = 4; /* default to 4 bits */