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riscv: dts: sophgo: Separate compatible specific for CV1800B soc

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As CV180x and CV181x have the identical layouts, it is OK to use the
cv1800b basic device tree for the whole series.
For CV1800B soc specific compatible, just move them out of the common
file.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Acked-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Inochi Amaoto 2023-10-19 07:18:51 +08:00 committed by Conor Dooley
parent d7b9202783
commit 5b5dce3951
2 changed files with 129 additions and 114 deletions
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123
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
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@ -3,121 +3,16 @@
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "cv18xx.dtsi"
/ {
compatible = "sophgo,cv1800b";
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
dma-noncoherent;
ranges;
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
&plic {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};

120
arch/riscv/boot/dts/sophgo/cv18xx.dtsi Normal file
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@ -0,0 +1,120 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
dma-noncoherent;
ranges;
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};