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arm64: dts: renesas: r8a779h0: Add IPMMU nodes

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Add device nodes for the main and cache I/O Memory Management Unit
(IPMMU) instances on the R-Car V4M (R8A779H0) SoC.

Add IPMMU main and cache nodes for R-Car R8A779H0 SoC.

Signed-off-by: Thanh Le <thanh.le.xv@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/b4701548e199ee2a72434bf73990557a63e13bd9.1713526951.git.geert+renesas@glider.be
This commit is contained in:
Thanh Le 2024-04-19 14:10:51 +02:00 committed by Geert Uytterhoeven
parent d28970ddd1
commit 5bd21a0009
1 changed files with 100 additions and 0 deletions
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100
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
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@ -1028,6 +1028,106 @@
status = "disabled";
};
ipmmu_rt0: iommu@ee480000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt1: iommu@ee4c0000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds0: iommu@eed00000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_hc: iommu@eed40000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_ir: iommu@eed80000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_vc: iommu@eedc0000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeedc0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_3dg: iommu@eee00000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_vi0: iommu@eee80000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_vi1: iommu@eeec0000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeeec0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_vip0: iommu@eef00000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779H0_PD_C4>;
#iommu-cells = <1>;
};
ipmmu_mm: iommu@eefc0000 {
compatible = "renesas,ipmmu-r8a779h0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeefc0000 0 0x20000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;