MT6795:
- add GCE, MMSYS, IOMMU and PMIC wrapper nodes - Enable PMIC combo, eMMC and SDIO support to the Sony Xperia M5 MT7622: - add SPI-NAND chip and interrupt support for switch node to the BPI-R64 MT7986: - add PWM, thermal, efuse, auxadc and thermal zone nodes - BPI-R3 enable WiFi leds and enable PWM - BPI-R3 reserve more space on NOR and NOR flash to be able to store bl2 uncompressed - BPI-R3 add PWM fan for cpu cooling MT8173: - fine tune the regulator of the eDP pannel - use EDID for eDP panel instead of hard coded type MT8183: - add quirk for GIC problem for Kukui based boards to make "pseudo NMIs" work - provide fimrware name to SCP MT8186: - add USB, SPMI, ADSP, Global Command Engine (GCE) nodes - add nodes to enable display support - add cache coherent interconnect - add dynamic voltage scaling for CPU and GPU MT8192: - enable Bluetooth on the Hayato board - add quirk for GIC problem for Kukui based boards to make "pseudo NMIs" work - add cpufreq node and video decoder - add dma-ranges needed by the IOMMU rework - Fine tune capacity-dmips-mhz MT8195: - add thermal zones and video decoder - enable PCI ports on cherry (e.g. Acer Chromebook Spin 513 CP513-2H) to enable WiFi and Bluetooth combo. - add quirk for GIC problem for Kukui based boards to make "pseudo NMIs" work MT8365: - add watchdog, PMIC, MMC, USB OTG, ethernet nodes - add Operation Performance Points - PSCI node and CPU idle support Several SoCs: - advertise L2 and L3 cache as unified - add chasss-type -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmSLBqcXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH44Hg/9GnoPeuq7clM7jBcrF1r1Q3yC p3ffpX+5l89Y4umi8duJ69TS83jdVWeQ7pT8Yavpcp5OW2XhRB2w+81JvwdegjVY wOksdzsIstPT9D0Q9NaKBnpdZXqhTMR6VT55K6echuPKNo1jwVNNweAe81na0Pka bm9cG1jTS6zZ5lqHclCx7rLc1RGx7DtpeMybFTwR25ohMsJ0k9UZnJrOop+WOesh SF69El0dmGefcBtSHGd7kGLEhOHy1IsJnvCpYyA03h/Z99fBtRY3fRBK+w/Z+BVk Q9zNN9UXe9U76JVTHz0/tfT6xaU2zX0ad+rTMTIx0yGmJNw7pu/bsUq3iuyqsxEr VjGEt/uNSK30MF7Tz0iSndyzRYu7lGy2JPI3WfnlNxlGsoIOTqw8E6dtichHUWsP fhh42EV9+3C2HLBGMvhGF2N5GBX1CQz7oJBUVVNNyFJVD5NE/9C+LX3rxTLfubEN mNmvJCVq3fujMTakOFFsHERl5znpyuQiL0QqEAn6CYnbsa9WDRqqP34dWMscsOTF 16TtS8Lyy70Sv7yfy4ym8O6w1DnXQ1SkE+qpSk/TmYCbyrbaHaQx+tb3CaMb1wQm xgtejqIo5owBQnVAgJjUTtzwj8md+0AlwyyzLi+ZSFwzSPAijGijHEf7lIZTV300 9/cen7u8DneBE47Nko0= =729t -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSSEyIACgkQYKtH/8kJ Uid37A//fHVhFmB75cpMOCsz+dD4pOs01UAZs8GKa/EkBMahrB4ts9DsLtWbhjIR NxxDFStQYlv6HXsHZkprg7nkx/W1NcmqX90tzP1JStC741WbC6pfJ3esaTuIogaA tuogV1aOGWGDBD0Kz2L1Uwn9LfXbQMQW24C3s7qORWg0ZJ3UjL8Av/JIr2xqg8t3 MAp6f1tpvFKa2YBYSTjY7VdgcLM3ZKS6fsWWzBVaNnU+a+4/NEXtiwuPphhJ0aWX HCie1S77fs1Kwew7aticdKitYClttn7ze21R15q0TFUj46MbXSPgG9syuDXM0ZqS de68APcL+UzZe4JUJnyVLrK2i9UQ7Y4NLGJf7KMQTma6MfFMCfS4IN9OydwYcnMt vb7DUPMi1N5eaQRld78pdAo5yBuGr1C4ZZc5pqku8Z5InMIjo9K+RT+jRXb47vfu gyT+O8OHXQEknzieGNRZASO6vrvN7ywOR/Mjh7djDU5P83CPFy9ShsvDPmq6mKX0 vEgaC+0IinyXmpL8kUm9h7PRnux3HHAbST7h9fWqmbqABAqTiybCn6+VJqAz971w faNAEV6snPsBPeN3a9+oPh+oLClRSaA5YG/u3kWx5+F+FogVExMpc6A7tKNLJYSC M8S2E/pzsb69uwvJK6Z54Qk6ihherE/SPOdpdj0SC61YEeUrr4s= =Jd/t -----END PGP SIGNATURE----- Merge tag 'v6.4-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/dt MT6795: - add GCE, MMSYS, IOMMU and PMIC wrapper nodes - Enable PMIC combo, eMMC and SDIO support to the Sony Xperia M5 MT7622: - add SPI-NAND chip and interrupt support for switch node to the BPI-R64 MT7986: - add PWM, thermal, efuse, auxadc and thermal zone nodes - BPI-R3 enable WiFi leds and enable PWM - BPI-R3 reserve more space on NOR and NOR flash to be able to store bl2 uncompressed - BPI-R3 add PWM fan for cpu cooling MT8173: - fine tune the regulator of the eDP pannel - use EDID for eDP panel instead of hard coded type MT8183: - add quirk for GIC problem for Kukui based boards to make "pseudo NMIs" work - provide fimrware name to SCP MT8186: - add USB, SPMI, ADSP, Global Command Engine (GCE) nodes - add nodes to enable display support - add cache coherent interconnect - add dynamic voltage scaling for CPU and GPU MT8192: - enable Bluetooth on the Hayato board - add quirk for GIC problem for Kukui based boards to make "pseudo NMIs" work - add cpufreq node and video decoder - add dma-ranges needed by the IOMMU rework - Fine tune capacity-dmips-mhz MT8195: - add thermal zones and video decoder - enable PCI ports on cherry (e.g. Acer Chromebook Spin 513 CP513-2H) to enable WiFi and Bluetooth combo. - add quirk for GIC problem for Kukui based boards to make "pseudo NMIs" work MT8365: - add watchdog, PMIC, MMC, USB OTG, ethernet nodes - add Operation Performance Points - PSCI node and CPU idle support Several SoCs: - advertise L2 and L3 cache as unified - add chasss-type * tag 'v6.4-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (51 commits) arm64: dts: mt7986: increase bl2 partition on NAND of Bananapi R3 arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts arm64: dts: mt7986: add thermal-zones arm64: dts: mt7986: add thermal and efuse arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz arm64: dts: mediatek: mt8192: Add missing dma-ranges to soc node arm64: dts: mediatek: mt8183: kukui: Add scp firmware-name arm64: dts: mt8195: Add video decoder node arm64: dts: mt8192: Add video-codec nodes arm64: dts: mediatek: Add cpufreq nodes for MT8192 arm64: dts: mediatek: mt8173-elm: remove panel model number in DT arm64: dts: mt7986: use size of reserved partition for bl2 arm64: dts: mt8173: Power on panel regulator on boot arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3 arm64: dts: mt7986: add PWM to BPI-R3 arm64: dts: mt7986: add PWM ... Link: https://lore.kernel.org/r/27843c96-142e-930e-33b2-b634182e7cfa@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
5bfea833dd
@ -11,6 +11,7 @@
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/ {
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model = "MediaTek MT2712 evaluation board";
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chassis-type = "embedded";
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compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
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aliases {
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284
arch/arm64/boot/dts/mediatek/mt6331.dtsi
Normal file
284
arch/arm64/boot/dts/mediatek/mt6331.dtsi
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@ -0,0 +1,284 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2023 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/input/input.h>
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&pwrap {
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pmic: mt6331 {
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compatible = "mediatek,mt6331";
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interrupt-controller;
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#interrupt-cells = <2>;
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mt6331regulator: mt6331regulator {
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compatible = "mediatek,mt6331-regulator";
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mt6331_vdvfs11_reg: buck-vdvfs11 {
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regulator-name = "vdvfs11";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1493750>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <0>;
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regulator-allowed-modes = <0 1>;
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regulator-always-on;
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};
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mt6331_vdvfs12_reg: buck-vdvfs12 {
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regulator-name = "vdvfs12";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1493750>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <0>;
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regulator-allowed-modes = <0 1>;
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regulator-always-on;
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};
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mt6331_vdvfs13_reg: buck-vdvfs13 {
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regulator-name = "vdvfs13";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1493750>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <0>;
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regulator-allowed-modes = <0 1>;
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regulator-always-on;
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};
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mt6331_vdvfs14_reg: buck-vdvfs14 {
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regulator-name = "vdvfs14";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1493750>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <0>;
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regulator-allowed-modes = <0 1>;
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regulator-always-on;
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};
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mt6331_vcore2_reg: buck-vcore2 {
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regulator-name = "vcore2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1493750>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <0>;
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regulator-allowed-modes = <0 1>;
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regulator-always-on;
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};
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mt6331_vio18_reg: buck-vio18 {
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regulator-name = "vio18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <0>;
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regulator-allowed-modes = <0 1>;
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regulator-always-on;
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};
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mt6331_vtcxo1_reg: ldo-vtcxo1 {
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regulator-name = "vtcxo1";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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regulator-boot-on;
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};
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mt6331_vtcxo2_reg: ldo-vtcxo2 {
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regulator-name = "vtcxo2";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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regulator-boot-on;
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};
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mt6331_avdd32_aud_reg: ldo-avdd32aud {
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regulator-name = "avdd32_aud";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <3200000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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regulator-boot-on;
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};
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mt6331_vauxa32_reg: ldo-vauxa32 {
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regulator-name = "vauxa32";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <3200000>;
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regulator-ramp-delay = <0>;
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};
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mt6331_vcama_reg: ldo-vcama {
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regulator-name = "vcama";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <2800000>;
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regulator-ramp-delay = <0>;
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};
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mt6331_vio28_reg: ldo-vio28 {
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regulator-name = "vio28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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regulator-boot-on;
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};
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mt6331_vcamaf_reg: ldo-vcamaf {
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regulator-name = "vcam_af";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-ramp-delay = <0>;
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};
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mt6331_vmc_reg: ldo-vmc {
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regulator-name = "vmc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-ramp-delay = <0>;
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};
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mt6331_vmch_reg: ldo-vmch {
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regulator-name = "vmch";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-ramp-delay = <0>;
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};
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mt6331_vemc33_reg: ldo-vemc33 {
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regulator-name = "vemc33";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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mt6331_vgp1_reg: ldo-vgp1 {
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regulator-name = "vgp1";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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mt6331_vsim1_reg: ldo-vsim1 {
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regulator-name = "vsim1";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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mt6331_vsim2_reg: ldo-vsim2 {
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regulator-name = "vsim2";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-ramp-delay = <0>;
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};
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mt6331_vmipi_reg: ldo-vmipi {
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regulator-name = "vmipi";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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mt6331_vibr_reg: ldo-vibr {
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regulator-name = "vibr";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-ramp-delay = <0>;
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};
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mt6331_vgp4_reg: ldo-vgp4 {
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regulator-name = "vgp4";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <2200000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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mt6331_vcamd_reg: ldo-vcamd {
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regulator-name = "vcamd";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1500000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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mt6331_vusb10_reg: ldo-vusb10 {
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regulator-name = "vusb";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1300000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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regulator-boot-on;
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};
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mt6331_vcamio_reg: ldo-vcamio {
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regulator-name = "vcam_io";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1800000>;
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regulator-ramp-delay = <0>;
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};
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mt6331_vsram_reg: ldo-vsram {
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regulator-name = "vsram";
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regulator-min-microvolt = <1012500>;
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regulator-max-microvolt = <1012500>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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regulator-boot-on;
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};
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mt6331_vgp2_reg: ldo-vgp2 {
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regulator-name = "vgp2";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1500000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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regulator-boot-on;
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};
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mt6331_vgp3_reg: ldo-vgp3 {
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regulator-name = "vgp3";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1800000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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mt6331_vrtc_reg: ldo-vrtc {
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regulator-name = "vrtc";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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mt6331_vdig18_reg: ldo-vdig18 {
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regulator-name = "dvdd18_dig";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-ramp-delay = <0>;
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regulator-always-on;
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};
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};
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mt6331rtc: mt6331rtc {
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compatible = "mediatek,mt6331-rtc";
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};
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mt6331keys: mt6331keys {
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compatible = "mediatek,mt6331-keys";
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power {
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linux,keycodes = <KEY_POWER>;
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wakeup-source;
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};
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home {
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linux,keycodes = <KEY_HOME>;
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};
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};
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};
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};
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@ -9,6 +9,7 @@
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/ {
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model = "MediaTek MT6755 EVB";
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chassis-type = "embedded";
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compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
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aliases {
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@ -10,6 +10,7 @@
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/ {
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model = "MediaTek MT6779 EVB";
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chassis-type = "embedded";
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compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
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aliases {
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@ -9,6 +9,7 @@
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/ {
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model = "MediaTek MT6795 Evaluation Board";
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chassis-type = "embedded";
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compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
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aliases {
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "mt6795.dtsi"
|
||||
#include "mt6331.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sony Xperia M5";
|
||||
@ -16,6 +17,7 @@
|
||||
aliases {
|
||||
mmc0 = &mmc0;
|
||||
mmc1 = &mmc1;
|
||||
mmc2 = &mmc2;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
@ -132,7 +134,97 @@
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
/* eMMC controller */
|
||||
mediatek,latch-ck = <0x14>; /* hs400 */
|
||||
mediatek,hs200-cmd-int-delay = <1>;
|
||||
mediatek,hs400-cmd-int-delay = <1>;
|
||||
mediatek,hs400-ds-dly3 = <0x1a>;
|
||||
non-removable;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
pinctrl-1 = <&mmc0_pins_uhs>;
|
||||
vmmc-supply = <&mt6331_vemc33_reg>;
|
||||
vqmmc-supply = <&mt6331_vio18_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
/* MicroSD card slot */
|
||||
vmmc-supply = <&mt6331_vmc_reg>;
|
||||
vqmmc-supply = <&mt6331_vmch_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
/* SDIO WiFi on MMC2 */
|
||||
vmmc-supply = <&mt6331_vmc_reg>;
|
||||
vqmmc-supply = <&mt6331_vmch_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
mmc0_pins_default: emmc-sdr-pins {
|
||||
pins-cmd-dat {
|
||||
pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
|
||||
<PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
|
||||
<PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
|
||||
<PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
|
||||
<PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
|
||||
<PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
|
||||
<PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
|
||||
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
|
||||
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins-clk {
|
||||
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins-rst {
|
||||
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_uhs: emmc-uhs-pins {
|
||||
pins-cmd-dat {
|
||||
pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
|
||||
<PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
|
||||
<PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
|
||||
<PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
|
||||
<PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
|
||||
<PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
|
||||
<PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
|
||||
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
|
||||
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins-clk {
|
||||
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins-rst {
|
||||
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins-ds {
|
||||
pinmux = <PINMUX_GPIO164__FUNC_MSDC0_DSL>;
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
};
|
||||
|
||||
nfc_pins: nfc-pins {
|
||||
pins-irq {
|
||||
pinmux = <PINMUX_GPIO3__FUNC_GPIO3>;
|
||||
@ -239,6 +331,15 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pmic {
|
||||
/*
|
||||
* Smartphones, including the Xperia M5, are equipped with a companion
|
||||
* MT6332 PMIC: when this is present, the main MT6331 PMIC will fire
|
||||
* an interrupt on the companion, so we use the MT6332 IRQ GPIO.
|
||||
*/
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -7,6 +7,8 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
|
||||
#include <dt-bindings/gce/mediatek,mt6795-gce.h>
|
||||
#include <dt-bindings/memory/mt6795-larb-port.h>
|
||||
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
|
||||
#include <dt-bindings/power/mt6795-power.h>
|
||||
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
|
||||
@ -372,6 +374,17 @@
|
||||
clocks = <&system_clk>, <&clk32k>;
|
||||
};
|
||||
|
||||
pwrap: pwrap@1000d000 {
|
||||
compatible = "mediatek,mt6795-pwrap";
|
||||
reg = <0 0x1000d000 0 0x1000>;
|
||||
reg-names = "pwrap";
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>;
|
||||
reset-names = "pwrap";
|
||||
clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>;
|
||||
clock-names = "spi", "wrap";
|
||||
};
|
||||
|
||||
sysirq: intpol-controller@10200620 {
|
||||
compatible = "mediatek,mt6795-sysirq",
|
||||
"mediatek,mt6577-sysirq";
|
||||
@ -389,6 +402,17 @@
|
||||
clock-names = "clk13m";
|
||||
};
|
||||
|
||||
iommu: iommu@10205000 {
|
||||
compatible = "mediatek,mt6795-m4u";
|
||||
reg = <0 0x10205000 0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_M4U>;
|
||||
clock-names = "bclk";
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
|
||||
mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
|
||||
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
apmixedsys: syscon@10209000 {
|
||||
compatible = "mediatek,mt6795-apmixedsys", "syscon";
|
||||
reg = <0 0x10209000 0 0x1000>;
|
||||
@ -401,6 +425,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gce: mailbox@10212000 {
|
||||
compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce";
|
||||
reg = <0 0x10212000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_GCE>;
|
||||
clock-names = "gce";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10221000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
@ -644,16 +677,77 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt6795-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
|
||||
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
|
||||
};
|
||||
|
||||
larb0: larb@14021000 {
|
||||
compatible = "mediatek,mt6795-smi-larb";
|
||||
reg = <0 0x14021000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>;
|
||||
clock-names = "apb", "smi";
|
||||
mediatek,smi = <&smi_common>;
|
||||
mediatek,larb-id = <0>;
|
||||
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
|
||||
};
|
||||
|
||||
smi_common: smi@14022000 {
|
||||
compatible = "mediatek,mt6795-smi-common";
|
||||
reg = <0 0x14022000 0 0x1000>;
|
||||
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
|
||||
clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>;
|
||||
clock-names = "apb", "smi";
|
||||
};
|
||||
|
||||
larb2: larb@15001000 {
|
||||
compatible = "mediatek,mt6795-smi-larb";
|
||||
reg = <0 0x15001000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>;
|
||||
clock-names = "apb", "smi";
|
||||
mediatek,smi = <&smi_common>;
|
||||
mediatek,larb-id = <2>;
|
||||
power-domains = <&spm MT6795_POWER_DOMAIN_ISP>;
|
||||
};
|
||||
|
||||
vdecsys: clock-controller@16000000 {
|
||||
compatible = "mediatek,mt6795-vdecsys";
|
||||
reg = <0 0x16000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
larb1: larb@16010000 {
|
||||
compatible = "mediatek,mt6795-smi-larb";
|
||||
reg = <0 0x16010000 0 0x1000>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
mediatek,larb-id = <1>;
|
||||
clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>;
|
||||
clock-names = "apb", "smi";
|
||||
power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>;
|
||||
};
|
||||
|
||||
vencsys: clock-controller@18000000 {
|
||||
compatible = "mediatek,mt6795-vencsys";
|
||||
reg = <0 0x18000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
larb3: larb@18001000 {
|
||||
compatible = "mediatek,mt6795-smi-larb";
|
||||
reg = <0 0x18001000 0 0x1000>;
|
||||
clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>;
|
||||
clock-names = "apb", "smi";
|
||||
mediatek,smi = <&smi_common>;
|
||||
mediatek,larb-id = <3>;
|
||||
power-domains = <&spm MT6795_POWER_DOMAIN_VENC>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT6797 Evaluation Board";
|
||||
chassis-type = "embedded";
|
||||
compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
/ {
|
||||
model = "Mediatek X20 Development Board";
|
||||
chassis-type = "embedded";
|
||||
compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
|
||||
/ {
|
||||
model = "Bananapi BPI-R64";
|
||||
chassis-type = "embedded";
|
||||
compatible = "bananapi,bpi-r64", "mediatek,mt7622";
|
||||
|
||||
aliases {
|
||||
@ -150,6 +151,10 @@
|
||||
switch@0 {
|
||||
compatible = "mediatek,mt7531";
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpios = <&pio 54 0>;
|
||||
|
||||
ports {
|
||||
@ -248,14 +253,42 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&nor_flash {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_nor_pins>;
|
||||
status = "disabled";
|
||||
&bch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&snfi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&serial_nand_pins>;
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
nand-ecc-engine = <&snfi>;
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "bl2";
|
||||
reg = <0x0 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "fip";
|
||||
reg = <0x80000 0x200000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
ubi: partition@280000 {
|
||||
label = "ubi";
|
||||
reg = <0x280000 0x7d80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7622 RFB1 board";
|
||||
chassis-type = "embedded";
|
||||
compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -101,6 +101,7 @@
|
||||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -29,13 +29,13 @@
|
||||
|
||||
partition@0 {
|
||||
label = "bl2";
|
||||
reg = <0x0 0x80000>;
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
partition@100000 {
|
||||
label = "reserved";
|
||||
reg = <0x80000 0x300000>;
|
||||
reg = <0x100000 0x280000>;
|
||||
};
|
||||
|
||||
partition@380000 {
|
||||
|
||||
@ -27,15 +27,10 @@
|
||||
|
||||
partition@0 {
|
||||
label = "bl2";
|
||||
reg = <0x0 0x20000>;
|
||||
reg = <0x0 0x40000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@20000 {
|
||||
label = "reserved";
|
||||
reg = <0x20000 0x20000>;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x40000 0x40000>;
|
||||
|
||||
@ -16,6 +16,7 @@
|
||||
|
||||
/ {
|
||||
model = "Bananapi BPI-R3";
|
||||
chassis-type = "embedded";
|
||||
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
|
||||
|
||||
aliases {
|
||||
@ -37,6 +38,15 @@
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
#cooling-cells = <2>;
|
||||
/* cooling level (0, 1, 2) - pwm inverted */
|
||||
cooling-levels = <255 96 0>;
|
||||
pwms = <&pwm 0 10000 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
@ -132,6 +142,28 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
cooling-maps {
|
||||
cpu-active-high {
|
||||
/* active: set fan to cooling level 2 */
|
||||
cooling-device = <&fan 2 2>;
|
||||
trip = <&cpu_trip_active_high>;
|
||||
};
|
||||
|
||||
cpu-active-low {
|
||||
/* active: set fan to cooling level 1 */
|
||||
cooling-device = <&fan 1 1>;
|
||||
trip = <&cpu_trip_active_low>;
|
||||
};
|
||||
|
||||
cpu-passive {
|
||||
/* passive: set fan to cooling level 0 */
|
||||
cooling-device = <&fan 0 0>;
|
||||
trip = <&cpu_trip_passive>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
@ -274,6 +306,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0", "pwm1_0";
|
||||
};
|
||||
};
|
||||
|
||||
spi_flash_pins: spi-flash-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
@ -344,6 +383,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
@ -446,5 +491,9 @@
|
||||
pinctrl-names = "default", "dbdc";
|
||||
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
|
||||
pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
|
||||
|
||||
led {
|
||||
led-active-low;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7986a RFB";
|
||||
chassis-type = "embedded";
|
||||
compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -240,6 +240,20 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@10048000 {
|
||||
compatible = "mediatek,mt7986-pwm";
|
||||
reg = <0 0x10048000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#pwm-cells = <2>;
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
||||
<&infracfg CLK_INFRA_PWM_STA>,
|
||||
<&infracfg CLK_INFRA_PWM1_CK>,
|
||||
<&infracfg CLK_INFRA_PWM2_CK>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@11002000 {
|
||||
compatible = "mediatek,mt7986-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
@ -323,6 +337,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
auxadc: adc@1100d000 {
|
||||
compatible = "mediatek,mt7986-auxadc";
|
||||
reg = <0 0x1100d000 0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
|
||||
clock-names = "main";
|
||||
#io-channel-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssusb: usb@11200000 {
|
||||
compatible = "mediatek,mt7986-xhci",
|
||||
"mediatek,mtk-xhci";
|
||||
@ -361,6 +384,21 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal: thermal@1100c800 {
|
||||
#thermal-sensor-cells = <1>;
|
||||
compatible = "mediatek,mt7986-thermal";
|
||||
reg = <0 0x1100c800 0 0x800>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_THERM_CK>,
|
||||
<&infracfg CLK_INFRA_ADC_26M_CK>,
|
||||
<&infracfg CLK_INFRA_ADC_FRC_CK>;
|
||||
clock-names = "therm", "auxadc", "adc_32k";
|
||||
mediatek,auxadc = <&auxadc>;
|
||||
mediatek,apmixedsys = <&apmixedsys>;
|
||||
nvmem-cells = <&thermal_calibration>;
|
||||
nvmem-cell-names = "calibration-data";
|
||||
};
|
||||
|
||||
pcie: pcie@11280000 {
|
||||
compatible = "mediatek,mt7986-pcie",
|
||||
"mediatek,mt8192-pcie";
|
||||
@ -412,6 +450,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
efuse: efuse@11d00000 {
|
||||
compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
|
||||
reg = <0 0x11d00000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
thermal_calibration: calib@274 {
|
||||
reg = <0x274 0xc>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_phy: t-phy@11e10000 {
|
||||
compatible = "mediatek,mt7986-tphy",
|
||||
"mediatek,generic-tphy-v2";
|
||||
@ -554,4 +603,31 @@
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&thermal 0>;
|
||||
|
||||
trips {
|
||||
cpu_trip_active_high: active-high {
|
||||
temperature = <115000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_active_low: active-low {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_passive: passive {
|
||||
temperature = <40000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7986b RFB";
|
||||
chassis-type = "embedded";
|
||||
compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
|
||||
/ {
|
||||
model = "Pumpkin MT8167";
|
||||
chassis-type = "embedded";
|
||||
compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
|
||||
|
||||
memory@40000000 {
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
|
||||
/ {
|
||||
model = "Google Hanawl";
|
||||
chassis-type = "laptop";
|
||||
compatible = "google,hana-rev7", "mediatek,mt8173";
|
||||
};
|
||||
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
|
||||
/ {
|
||||
model = "Google Hana";
|
||||
chassis-type = "laptop";
|
||||
compatible = "google,hana-rev6", "google,hana-rev5",
|
||||
"google,hana-rev4", "google,hana-rev3",
|
||||
"google,hana", "mediatek,mt8173";
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
|
||||
/ {
|
||||
model = "Google Elm";
|
||||
chassis-type = "laptop";
|
||||
compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
|
||||
"google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
|
||||
"google,elm", "mediatek,mt8173";
|
||||
|
||||
@ -96,6 +96,8 @@
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
off-on-delay-us = <500000>;
|
||||
gpio = <&pio 41 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&panel_fixed_pins>;
|
||||
@ -285,7 +287,7 @@
|
||||
|
||||
aux-bus {
|
||||
panel: panel {
|
||||
compatible = "lg,lp120up1";
|
||||
compatible = "edp-panel";
|
||||
power-supply = <&panel_fixed_3v3>;
|
||||
backlight = <&backlight>;
|
||||
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT8173 evaluation board";
|
||||
chassis-type = "embedded";
|
||||
compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT8183 evaluation board";
|
||||
chassis-type = "embedded";
|
||||
compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
/ {
|
||||
model = "Google burnet board";
|
||||
chassis-type = "convertible";
|
||||
compatible = "google,burnet", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
/ {
|
||||
model = "Google damu board";
|
||||
chassis-type = "convertible";
|
||||
compatible = "google,damu", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
/ {
|
||||
model = "Google juniper sku16 board";
|
||||
chassis-type = "convertible";
|
||||
compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek kakadu board sku22";
|
||||
chassis-type = "tablet";
|
||||
compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
|
||||
"google,kakadu", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek kakadu board";
|
||||
chassis-type = "tablet";
|
||||
compatible = "google,kakadu-rev3", "google,kakadu-rev2",
|
||||
"google,kakadu", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek kodama sku16 board";
|
||||
chassis-type = "tablet";
|
||||
compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek kodama sku272 board";
|
||||
chassis-type = "tablet";
|
||||
compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek kodama sku288 board";
|
||||
chassis-type = "tablet";
|
||||
compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek krane sku0 board";
|
||||
chassis-type = "tablet";
|
||||
compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek krane sku176 board";
|
||||
chassis-type = "tablet";
|
||||
compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
|
||||
@ -292,6 +292,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gic {
|
||||
mediatek,broken-save-restore-fw;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&mt6358_vgpu_reg>;
|
||||
};
|
||||
@ -822,6 +826,8 @@
|
||||
|
||||
&scp {
|
||||
status = "okay";
|
||||
|
||||
firmware-name = "mediatek/mt8183/scp.img";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&scp_pins>;
|
||||
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT8186 evaluation board";
|
||||
chassis-type = "embedded";
|
||||
compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
|
||||
|
||||
aliases {
|
||||
|
||||
@ -5,6 +5,7 @@
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
#include <dt-bindings/gce/mt8186-gce.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/memory/mt8186-memory-port.h>
|
||||
@ -19,6 +20,308 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ovl0 = &ovl0;
|
||||
ovl_2l0 = &ovl_2l0;
|
||||
rdma0 = &rdma0;
|
||||
rdma1 = &rdma1;
|
||||
};
|
||||
|
||||
cci: cci {
|
||||
compatible = "mediatek,mt8186-cci";
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cci", "intermediate";
|
||||
operating-points-v2 = <&cci_opp>;
|
||||
};
|
||||
|
||||
cci_opp: opp-table-cci {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
cci_opp_0: opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <600000>;
|
||||
};
|
||||
|
||||
cci_opp_1: opp-560000000 {
|
||||
opp-hz = /bits/ 64 <560000000>;
|
||||
opp-microvolt = <675000>;
|
||||
};
|
||||
|
||||
cci_opp_2: opp-612000000 {
|
||||
opp-hz = /bits/ 64 <612000000>;
|
||||
opp-microvolt = <693750>;
|
||||
};
|
||||
|
||||
cci_opp_3: opp-682000000 {
|
||||
opp-hz = /bits/ 64 <682000000>;
|
||||
opp-microvolt = <718750>;
|
||||
};
|
||||
|
||||
cci_opp_4: opp-752000000 {
|
||||
opp-hz = /bits/ 64 <752000000>;
|
||||
opp-microvolt = <743750>;
|
||||
};
|
||||
|
||||
cci_opp_5: opp-822000000 {
|
||||
opp-hz = /bits/ 64 <822000000>;
|
||||
opp-microvolt = <768750>;
|
||||
};
|
||||
|
||||
cci_opp_6: opp-875000000 {
|
||||
opp-hz = /bits/ 64 <875000000>;
|
||||
opp-microvolt = <781250>;
|
||||
};
|
||||
|
||||
cci_opp_7: opp-927000000 {
|
||||
opp-hz = /bits/ 64 <927000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
||||
cci_opp_8: opp-980000000 {
|
||||
opp-hz = /bits/ 64 <980000000>;
|
||||
opp-microvolt = <818750>;
|
||||
};
|
||||
|
||||
cci_opp_9: opp-1050000000 {
|
||||
opp-hz = /bits/ 64 <1050000000>;
|
||||
opp-microvolt = <843750>;
|
||||
};
|
||||
|
||||
cci_opp_10: opp-1120000000 {
|
||||
opp-hz = /bits/ 64 <1120000000>;
|
||||
opp-microvolt = <862500>;
|
||||
};
|
||||
|
||||
cci_opp_11: opp-1155000000 {
|
||||
opp-hz = /bits/ 64 <1155000000>;
|
||||
opp-microvolt = <887500>;
|
||||
};
|
||||
|
||||
cci_opp_12: opp-1190000000 {
|
||||
opp-hz = /bits/ 64 <1190000000>;
|
||||
opp-microvolt = <906250>;
|
||||
};
|
||||
|
||||
cci_opp_13: opp-1260000000 {
|
||||
opp-hz = /bits/ 64 <1260000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
|
||||
cci_opp_14: opp-1330000000 {
|
||||
opp-hz = /bits/ 64 <1330000000>;
|
||||
opp-microvolt = <993750>;
|
||||
};
|
||||
|
||||
cci_opp_15: opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-microvolt = <1031250>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_opp: opp-table-cluster0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <600000>;
|
||||
required-opps = <&cci_opp_0>;
|
||||
};
|
||||
|
||||
opp-774000000 {
|
||||
opp-hz = /bits/ 64 <774000000>;
|
||||
opp-microvolt = <675000>;
|
||||
required-opps = <&cci_opp_1>;
|
||||
};
|
||||
|
||||
opp-875000000 {
|
||||
opp-hz = /bits/ 64 <875000000>;
|
||||
opp-microvolt = <700000>;
|
||||
required-opps = <&cci_opp_2>;
|
||||
};
|
||||
|
||||
opp-975000000 {
|
||||
opp-hz = /bits/ 64 <975000000>;
|
||||
opp-microvolt = <725000>;
|
||||
required-opps = <&cci_opp_3>;
|
||||
};
|
||||
|
||||
opp-1075000000 {
|
||||
opp-hz = /bits/ 64 <1075000000>;
|
||||
opp-microvolt = <750000>;
|
||||
required-opps = <&cci_opp_4>;
|
||||
};
|
||||
|
||||
opp-1175000000 {
|
||||
opp-hz = /bits/ 64 <1175000000>;
|
||||
opp-microvolt = <775000>;
|
||||
required-opps = <&cci_opp_5>;
|
||||
};
|
||||
|
||||
opp-1275000000 {
|
||||
opp-hz = /bits/ 64 <1275000000>;
|
||||
opp-microvolt = <800000>;
|
||||
required-opps = <&cci_opp_6>;
|
||||
};
|
||||
|
||||
opp-1375000000 {
|
||||
opp-hz = /bits/ 64 <1375000000>;
|
||||
opp-microvolt = <825000>;
|
||||
required-opps = <&cci_opp_7>;
|
||||
};
|
||||
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <856250>;
|
||||
required-opps = <&cci_opp_8>;
|
||||
};
|
||||
|
||||
opp-1618000000 {
|
||||
opp-hz = /bits/ 64 <1618000000>;
|
||||
opp-microvolt = <875000>;
|
||||
required-opps = <&cci_opp_9>;
|
||||
};
|
||||
|
||||
opp-1666000000 {
|
||||
opp-hz = /bits/ 64 <1666000000>;
|
||||
opp-microvolt = <900000>;
|
||||
required-opps = <&cci_opp_10>;
|
||||
};
|
||||
|
||||
opp-1733000000 {
|
||||
opp-hz = /bits/ 64 <1733000000>;
|
||||
opp-microvolt = <925000>;
|
||||
required-opps = <&cci_opp_11>;
|
||||
};
|
||||
|
||||
opp-1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <950000>;
|
||||
required-opps = <&cci_opp_12>;
|
||||
};
|
||||
|
||||
opp-1866000000 {
|
||||
opp-hz = /bits/ 64 <1866000000>;
|
||||
opp-microvolt = <981250>;
|
||||
required-opps = <&cci_opp_13>;
|
||||
};
|
||||
|
||||
opp-1933000000 {
|
||||
opp-hz = /bits/ 64 <1933000000>;
|
||||
opp-microvolt = <1006250>;
|
||||
required-opps = <&cci_opp_14>;
|
||||
};
|
||||
|
||||
opp-2000000000 {
|
||||
opp-hz = /bits/ 64 <2000000000>;
|
||||
opp-microvolt = <1031250>;
|
||||
required-opps = <&cci_opp_15>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp-table-cluster1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-774000000 {
|
||||
opp-hz = /bits/ 64 <774000000>;
|
||||
opp-microvolt = <675000>;
|
||||
required-opps = <&cci_opp_0>;
|
||||
};
|
||||
|
||||
opp-835000000 {
|
||||
opp-hz = /bits/ 64 <835000000>;
|
||||
opp-microvolt = <693750>;
|
||||
required-opps = <&cci_opp_1>;
|
||||
};
|
||||
|
||||
opp-919000000 {
|
||||
opp-hz = /bits/ 64 <919000000>;
|
||||
opp-microvolt = <718750>;
|
||||
required-opps = <&cci_opp_2>;
|
||||
};
|
||||
|
||||
opp-1002000000 {
|
||||
opp-hz = /bits/ 64 <1002000000>;
|
||||
opp-microvolt = <743750>;
|
||||
required-opps = <&cci_opp_3>;
|
||||
};
|
||||
|
||||
opp-1085000000 {
|
||||
opp-hz = /bits/ 64 <1085000000>;
|
||||
opp-microvolt = <775000>;
|
||||
required-opps = <&cci_opp_4>;
|
||||
};
|
||||
|
||||
opp-1169000000 {
|
||||
opp-hz = /bits/ 64 <1169000000>;
|
||||
opp-microvolt = <800000>;
|
||||
required-opps = <&cci_opp_5>;
|
||||
};
|
||||
|
||||
opp-1308000000 {
|
||||
opp-hz = /bits/ 64 <1308000000>;
|
||||
opp-microvolt = <843750>;
|
||||
required-opps = <&cci_opp_6>;
|
||||
};
|
||||
|
||||
opp-1419000000 {
|
||||
opp-hz = /bits/ 64 <1419000000>;
|
||||
opp-microvolt = <875000>;
|
||||
required-opps = <&cci_opp_7>;
|
||||
};
|
||||
|
||||
opp-1530000000 {
|
||||
opp-hz = /bits/ 64 <1530000000>;
|
||||
opp-microvolt = <912500>;
|
||||
required-opps = <&cci_opp_8>;
|
||||
};
|
||||
|
||||
opp-1670000000 {
|
||||
opp-hz = /bits/ 64 <1670000000>;
|
||||
opp-microvolt = <956250>;
|
||||
required-opps = <&cci_opp_9>;
|
||||
};
|
||||
|
||||
opp-1733000000 {
|
||||
opp-hz = /bits/ 64 <1733000000>;
|
||||
opp-microvolt = <981250>;
|
||||
required-opps = <&cci_opp_10>;
|
||||
};
|
||||
|
||||
opp-1796000000 {
|
||||
opp-hz = /bits/ 64 <1796000000>;
|
||||
opp-microvolt = <1012500>;
|
||||
required-opps = <&cci_opp_11>;
|
||||
};
|
||||
|
||||
opp-1860000000 {
|
||||
opp-hz = /bits/ 64 <1860000000>;
|
||||
opp-microvolt = <1037500>;
|
||||
required-opps = <&cci_opp_12>;
|
||||
};
|
||||
|
||||
opp-1923000000 {
|
||||
opp-hz = /bits/ 64 <1923000000>;
|
||||
opp-microvolt = <1062500>;
|
||||
required-opps = <&cci_opp_13>;
|
||||
};
|
||||
|
||||
cluster1_opp_14: opp-1986000000 {
|
||||
opp-hz = /bits/ 64 <1986000000>;
|
||||
opp-microvolt = <1093750>;
|
||||
required-opps = <&cci_opp_14>;
|
||||
};
|
||||
|
||||
cluster1_opp_15: opp-2050000000 {
|
||||
opp-hz = /bits/ 64 <2050000000>;
|
||||
opp-microvolt = <1118750>;
|
||||
required-opps = <&cci_opp_15>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -65,6 +368,11 @@
|
||||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2000000000>;
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
capacity-dmips-mhz = <382>;
|
||||
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
|
||||
i-cache-size = <32768>;
|
||||
@ -75,6 +383,7 @@
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
#cooling-cells = <2>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
@ -83,6 +392,11 @@
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2000000000>;
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
capacity-dmips-mhz = <382>;
|
||||
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
|
||||
i-cache-size = <32768>;
|
||||
@ -93,6 +407,7 @@
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
#cooling-cells = <2>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
@ -101,6 +416,11 @@
|
||||
reg = <0x200>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2000000000>;
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
capacity-dmips-mhz = <382>;
|
||||
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
|
||||
i-cache-size = <32768>;
|
||||
@ -111,6 +431,7 @@
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
#cooling-cells = <2>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
@ -119,6 +440,11 @@
|
||||
reg = <0x300>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2000000000>;
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
capacity-dmips-mhz = <382>;
|
||||
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
|
||||
i-cache-size = <32768>;
|
||||
@ -129,6 +455,7 @@
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
#cooling-cells = <2>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cpu4: cpu@400 {
|
||||
@ -137,6 +464,11 @@
|
||||
reg = <0x400>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2000000000>;
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
capacity-dmips-mhz = <382>;
|
||||
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
|
||||
i-cache-size = <32768>;
|
||||
@ -147,6 +479,7 @@
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
#cooling-cells = <2>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cpu5: cpu@500 {
|
||||
@ -155,6 +488,11 @@
|
||||
reg = <0x500>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2000000000>;
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
capacity-dmips-mhz = <382>;
|
||||
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
|
||||
i-cache-size = <32768>;
|
||||
@ -165,6 +503,7 @@
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
#cooling-cells = <2>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cpu6: cpu@600 {
|
||||
@ -173,6 +512,11 @@
|
||||
reg = <0x600>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2050000000>;
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
dynamic-power-coefficient = <335>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
|
||||
i-cache-size = <65536>;
|
||||
@ -183,6 +527,7 @@
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_1>;
|
||||
#cooling-cells = <2>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
cpu7: cpu@700 {
|
||||
@ -191,6 +536,11 @@
|
||||
reg = <0x700>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2050000000>;
|
||||
clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
dynamic-power-coefficient = <335>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
|
||||
i-cache-size = <65536>;
|
||||
@ -201,6 +551,7 @@
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_1>;
|
||||
#cooling-cells = <2>;
|
||||
mediatek,cci = <&cci>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
@ -250,6 +601,7 @@
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
next-level-cache = <&l3_0>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
l2_1: l2-cache1 {
|
||||
@ -259,6 +611,7 @@
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
next-level-cache = <&l3_0>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
l3_0: l3-cache {
|
||||
@ -294,6 +647,142 @@
|
||||
clock-output-names = "clk32k";
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table-gpu {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-299000000 {
|
||||
opp-hz = /bits/ 64 <299000000>;
|
||||
opp-microvolt = <612500>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-332000000 {
|
||||
opp-hz = /bits/ 64 <332000000>;
|
||||
opp-microvolt = <625000>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-366000000 {
|
||||
opp-hz = /bits/ 64 <366000000>;
|
||||
opp-microvolt = <637500>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <643750>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-434000000 {
|
||||
opp-hz = /bits/ 64 <434000000>;
|
||||
opp-microvolt = <656250>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-484000000 {
|
||||
opp-hz = /bits/ 64 <484000000>;
|
||||
opp-microvolt = <668750>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-535000000 {
|
||||
opp-hz = /bits/ 64 <535000000>;
|
||||
opp-microvolt = <687500>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-586000000 {
|
||||
opp-hz = /bits/ 64 <586000000>;
|
||||
opp-microvolt = <700000>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-637000000 {
|
||||
opp-hz = /bits/ 64 <637000000>;
|
||||
opp-microvolt = <712500>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-690000000 {
|
||||
opp-hz = /bits/ 64 <690000000>;
|
||||
opp-microvolt = <737500>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-743000000 {
|
||||
opp-hz = /bits/ 64 <743000000>;
|
||||
opp-microvolt = <756250>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-796000000 {
|
||||
opp-hz = /bits/ 64 <796000000>;
|
||||
opp-microvolt = <781250>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-850000000 {
|
||||
opp-hz = /bits/ 64 <850000000>;
|
||||
opp-microvolt = <800000>;
|
||||
opp-supported-hw = <0xff>;
|
||||
};
|
||||
|
||||
opp-900000000-3 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <850000>;
|
||||
opp-supported-hw = <0x8>;
|
||||
};
|
||||
|
||||
opp-900000000-4 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <837500>;
|
||||
opp-supported-hw = <0x10>;
|
||||
};
|
||||
|
||||
opp-900000000-5 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <825000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
};
|
||||
|
||||
opp-950000000-3 {
|
||||
opp-hz = /bits/ 64 <950000000>;
|
||||
opp-microvolt = <900000>;
|
||||
opp-supported-hw = <0x8>;
|
||||
};
|
||||
|
||||
opp-950000000-4 {
|
||||
opp-hz = /bits/ 64 <950000000>;
|
||||
opp-microvolt = <875000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
};
|
||||
|
||||
opp-950000000-5 {
|
||||
opp-hz = /bits/ 64 <950000000>;
|
||||
opp-microvolt = <850000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
};
|
||||
|
||||
opp-1000000000-3 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <950000>;
|
||||
opp-supported-hw = <0x8>;
|
||||
};
|
||||
|
||||
opp-1000000000-4 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <912500>;
|
||||
opp-supported-hw = <0x10>;
|
||||
};
|
||||
|
||||
opp-1000000000-5 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <875000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu-a55 {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
interrupt-parent = <&gic>;
|
||||
@ -412,7 +901,7 @@
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
power-domain@MT8186_POWER_DOMAIN_MFG1 {
|
||||
mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
|
||||
reg = <MT8186_POWER_DOMAIN_MFG1>;
|
||||
mediatek,infracfg = <&infracfg_ao>;
|
||||
#address-cells = <1>;
|
||||
@ -603,6 +1092,21 @@
|
||||
clock-names = "spi", "wrap";
|
||||
};
|
||||
|
||||
spmi: spmi@10015000 {
|
||||
compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
|
||||
reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>;
|
||||
reg-names = "pmif", "spmimst";
|
||||
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
|
||||
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
|
||||
<&topckgen CLK_TOP_SPMI_MST>;
|
||||
clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
|
||||
assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
|
||||
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
systimer: timer@10017000 {
|
||||
compatible = "mediatek,mt8186-timer",
|
||||
"mediatek,mt6765-timer";
|
||||
@ -611,6 +1115,15 @@
|
||||
clocks = <&clk13m>;
|
||||
};
|
||||
|
||||
gce: mailbox@1022c000 {
|
||||
compatible = "mediatek,mt8186-gce";
|
||||
reg = <0 0X1022c000 0 0x4000>;
|
||||
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
|
||||
clock-names = "gce";
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
scp: scp@10500000 {
|
||||
compatible = "mediatek,mt8186-scp";
|
||||
reg = <0 0x10500000 0 0x40000>,
|
||||
@ -619,6 +1132,22 @@
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
};
|
||||
|
||||
adsp: adsp@10680000 {
|
||||
compatible = "mediatek,mt8186-dsp";
|
||||
reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
|
||||
<0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
|
||||
reg-names = "cfg", "sram", "sec", "bus";
|
||||
clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;
|
||||
clock-names = "audiodsp", "adsp_bus";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
|
||||
<&topckgen CLK_TOP_ADSP_BUS>;
|
||||
assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
|
||||
mbox-names = "rx", "tx";
|
||||
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adsp_mailbox0: mailbox@10686000 {
|
||||
compatible = "mediatek,mt8186-adsp-mbox";
|
||||
#mbox-cells = <0>;
|
||||
@ -982,6 +1511,40 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssusb0: usb@11201000 {
|
||||
compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
|
||||
reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
clocks = <&topckgen CLK_TOP_USB_TOP>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
|
||||
<&infracfg_ao CLK_INFRA_AO_ICUSB>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
phys = <&u2port0 PHY_TYPE_USB2>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
usb_host0: usb@11200000 {
|
||||
compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
|
||||
reg = <0 0x11200000 0 0x1000>;
|
||||
reg-names = "mac";
|
||||
clocks = <&topckgen CLK_TOP_USB_TOP>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
|
||||
<&infracfg_ao CLK_INFRA_AO_ICUSB>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
|
||||
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,syscon-wakeup = <&pericfg 0x420 2>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt8186-mmc",
|
||||
"mediatek,mt8183-mmc";
|
||||
@ -1013,6 +1576,40 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssusb1: usb@11281000 {
|
||||
compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
|
||||
reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
|
||||
<&clk26m>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
|
||||
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
usb_host1: usb@11280000 {
|
||||
compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
|
||||
reg = <0 0x11280000 0 0x1000>;
|
||||
reg-names = "mac";
|
||||
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
|
||||
<&clk26m>,
|
||||
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
|
||||
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,syscon-wakeup = <&pericfg 0x424 2>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
u3phy0: t-phy@11c80000 {
|
||||
compatible = "mediatek,mt8186-tphy",
|
||||
"mediatek,generic-tphy-v2";
|
||||
@ -1058,6 +1655,11 @@
|
||||
reg = <0 0x11cb0000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpu_speedbin: gpu-speed-bin@59c {
|
||||
reg = <0x59c 0x4>;
|
||||
bits = <0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
mipi_tx0: dsi-phy@11cc0000 {
|
||||
@ -1090,6 +1692,10 @@
|
||||
<&spm MT8186_POWER_DOMAIN_MFG3>;
|
||||
power-domain-names = "core0", "core1";
|
||||
#cooling-cells = <2>;
|
||||
nvmem-cells = <&gpu_speedbin>;
|
||||
nvmem-cell-names = "speed-bin";
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
dynamic-power-coefficient = <4687>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1098,6 +1704,20 @@
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
|
||||
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
|
||||
};
|
||||
|
||||
mutex: mutex@14001000 {
|
||||
compatible = "mediatek,mt8186-disp-mutex";
|
||||
reg = <0 0x14001000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
|
||||
interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
|
||||
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
smi_common: smi@14002000 {
|
||||
@ -1131,6 +1751,45 @@
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
ovl0: ovl@14005000 {
|
||||
compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
|
||||
reg = <0 0x14005000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
ovl_2l0: ovl@14006000 {
|
||||
compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
|
||||
reg = <0 0x14006000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
|
||||
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
rdma0: rdma@14007000 {
|
||||
compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
|
||||
reg = <0 0x14007000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
color: color@14009000 {
|
||||
compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14009000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
dpi: dpi@1400a000 {
|
||||
compatible = "mediatek,mt8186-dpi";
|
||||
reg = <0 0x1400a000 0 0x1000>;
|
||||
@ -1148,6 +1807,52 @@
|
||||
};
|
||||
};
|
||||
|
||||
ccorr: ccorr@1400b000 {
|
||||
compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
|
||||
reg = <0 0x1400b000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
|
||||
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
aal: aal@1400c000 {
|
||||
compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL0>;
|
||||
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
gamma: gamma@1400d000 {
|
||||
compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
|
||||
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
postmask: postmask@1400e000 {
|
||||
compatible = "mediatek,mt8186-disp-postmask",
|
||||
"mediatek,mt8192-disp-postmask";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
|
||||
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
dither: dither@1400f000 {
|
||||
compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
|
||||
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
dsi0: dsi@14013000 {
|
||||
compatible = "mediatek,mt8186-dsi";
|
||||
reg = <0 0x14013000 0 0x1000>;
|
||||
@ -1181,6 +1886,16 @@
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
rdma1: rdma@1401f000 {
|
||||
compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
|
||||
reg = <0 0x1401f000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
||||
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
|
||||
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
|
||||
};
|
||||
|
||||
wpesys: clock-controller@14020000 {
|
||||
compatible = "mediatek,mt8186-wpesys";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
|
||||
@ -40,9 +40,90 @@
|
||||
>;
|
||||
};
|
||||
|
||||
&pio {
|
||||
bt_pins: bt-pins {
|
||||
pins-bt-kill {
|
||||
pinmux = <PINMUX_GPIO144__FUNC_GPIO144>;
|
||||
output-low;
|
||||
};
|
||||
|
||||
pins-bt-wake {
|
||||
pinmux = <PINMUX_GPIO22__FUNC_GPIO22>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pins-ap-wake-bt {
|
||||
pinmux = <PINMUX_GPIO168__FUNC_GPIO168>;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: uart1-pins {
|
||||
pins-rx {
|
||||
pinmux = <PINMUX_GPIO94__FUNC_URXD1>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pins-tx {
|
||||
pinmux = <PINMUX_GPIO95__FUNC_UTXD1>;
|
||||
};
|
||||
|
||||
pins-cts {
|
||||
pinmux = <PINMUX_GPIO166__FUNC_UCTS1>;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
pins-rts {
|
||||
pinmux = <PINMUX_GPIO167__FUNC_URTS1>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins_sleep: uart1-sleep-pins {
|
||||
pins-rx {
|
||||
pinmux = <PINMUX_GPIO94__FUNC_GPIO94>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pins-tx {
|
||||
pinmux = <PINMUX_GPIO95__FUNC_UTXD1>;
|
||||
};
|
||||
|
||||
pins-cts {
|
||||
pinmux = <PINMUX_GPIO166__FUNC_UCTS1>;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
pins-rts {
|
||||
pinmux = <PINMUX_GPIO167__FUNC_URTS1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
compatible = "hid-over-i2c";
|
||||
post-power-on-delay-ms = <10>;
|
||||
hid-descr-addr = <0x0001>;
|
||||
vdd-supply = <&pp3300_u>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
pinctrl-1 = <&uart1_pins_sleep>;
|
||||
/delete-property/ interrupts;
|
||||
interrupts-extended = <&gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<&pio 94 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
bluetooth {
|
||||
compatible = "realtek,rtl8822cs-bt";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bt_pins>;
|
||||
|
||||
enable-gpios = <&pio 144 GPIO_ACTIVE_HIGH>;
|
||||
device-wake-gpios = <&pio 168 GPIO_ACTIVE_HIGH>;
|
||||
host-wake-gpios = <&pio 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -275,6 +275,10 @@
|
||||
remote-endpoint = <&anx7625_in>;
|
||||
};
|
||||
|
||||
&gic {
|
||||
mediatek,broken-save-restore-fw;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&mt6315_7_vbuck1>;
|
||||
status = "okay";
|
||||
|
||||
@ -70,7 +70,8 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
capacity-dmips-mhz = <530>;
|
||||
performance-domains = <&performance 0>;
|
||||
capacity-dmips-mhz = <427>;
|
||||
};
|
||||
|
||||
cpu1: cpu@100 {
|
||||
@ -87,7 +88,8 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
capacity-dmips-mhz = <530>;
|
||||
performance-domains = <&performance 0>;
|
||||
capacity-dmips-mhz = <427>;
|
||||
};
|
||||
|
||||
cpu2: cpu@200 {
|
||||
@ -104,7 +106,8 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
capacity-dmips-mhz = <530>;
|
||||
performance-domains = <&performance 0>;
|
||||
capacity-dmips-mhz = <427>;
|
||||
};
|
||||
|
||||
cpu3: cpu@300 {
|
||||
@ -121,7 +124,8 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&l2_0>;
|
||||
capacity-dmips-mhz = <530>;
|
||||
performance-domains = <&performance 0>;
|
||||
capacity-dmips-mhz = <427>;
|
||||
};
|
||||
|
||||
cpu4: cpu@400 {
|
||||
@ -138,6 +142,7 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_1>;
|
||||
performance-domains = <&performance 1>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
@ -155,6 +160,7 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_1>;
|
||||
performance-domains = <&performance 1>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
@ -172,6 +178,7 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_1>;
|
||||
performance-domains = <&performance 1>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
@ -189,6 +196,7 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_1>;
|
||||
performance-domains = <&performance 1>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
@ -228,6 +236,7 @@
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
next-level-cache = <&l3_0>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
l2_1: l2-cache1 {
|
||||
@ -237,6 +246,7 @@
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
next-level-cache = <&l3_0>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
l3_0: l3-cache {
|
||||
@ -401,8 +411,15 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
|
||||
ranges;
|
||||
|
||||
performance: performance-controller@11bc10 {
|
||||
compatible = "mediatek,cpufreq-hw";
|
||||
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
|
||||
#performance-domain-cells = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@c000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <4>;
|
||||
@ -1625,6 +1642,65 @@
|
||||
power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
|
||||
};
|
||||
|
||||
vcodec_dec: video-codec@16000000 {
|
||||
compatible = "mediatek,mt8192-vcodec-dec";
|
||||
reg = <0 0x16000000 0 0x1000>;
|
||||
mediatek,scp = <&scp>;
|
||||
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0 0 0x16000000 0 0x26000>;
|
||||
|
||||
video-codec@10000 {
|
||||
compatible = "mediatek,mtk-vcodec-lat";
|
||||
reg = <0x0 0x10000 0 0x800>;
|
||||
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
|
||||
<&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
|
||||
};
|
||||
|
||||
video-codec@25000 {
|
||||
compatible = "mediatek,mtk-vcodec-core";
|
||||
reg = <0 0x25000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
|
||||
<&vdecsys CLK_VDEC_VDEC>,
|
||||
<&vdecsys CLK_VDEC_LAT>,
|
||||
<&vdecsys CLK_VDEC_LARB1>,
|
||||
<&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
|
||||
};
|
||||
};
|
||||
|
||||
larb5: larb@1600d000 {
|
||||
compatible = "mediatek,mt8192-smi-larb";
|
||||
reg = <0 0x1600d000 0 0x1000>;
|
||||
|
||||
@ -255,6 +255,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gic {
|
||||
mediatek,broken-save-restore-fw;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
mali-supply = <&mt6315_7_vbuck1>;
|
||||
@ -464,6 +468,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie1_pins_default>;
|
||||
};
|
||||
|
||||
&pio {
|
||||
mediatek,rsel-resistance-in-si-unit;
|
||||
pinctrl-names = "default";
|
||||
@ -852,6 +863,24 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_pins_default: pcie0-default-pins {
|
||||
pins-bus {
|
||||
pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
|
||||
<PINMUX_GPIO20__FUNC_PERSTN>,
|
||||
<PINMUX_GPIO21__FUNC_CLKREQN>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_pins_default: pcie1-default-pins {
|
||||
pins-bus {
|
||||
pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
|
||||
<PINMUX_GPIO23__FUNC_CLKREQN_1>,
|
||||
<PINMUX_GPIO24__FUNC_WAKEN_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pio_default: pio-default-pins {
|
||||
pins-wifi-enable {
|
||||
pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
|
||||
|
||||
@ -24,6 +24,8 @@
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
dp-intf0 = &dp_intf0;
|
||||
dp-intf1 = &dp_intf1;
|
||||
gce0 = &gce0;
|
||||
gce1 = &gce1;
|
||||
ethdr0 = ðdr0;
|
||||
@ -283,6 +285,7 @@
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
next-level-cache = <&l3_0>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
l2_1: l2-cache1 {
|
||||
@ -292,6 +295,7 @@
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
next-level-cache = <&l3_0>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
l3_0: l3-cache {
|
||||
@ -2366,6 +2370,76 @@
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
|
||||
};
|
||||
|
||||
video-codec@18000000 {
|
||||
compatible = "mediatek,mt8195-vcodec-dec";
|
||||
mediatek,scp = <&scp>;
|
||||
iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0 0x18000000 0 0x1000>,
|
||||
<0 0x18004000 0 0x1000>;
|
||||
ranges = <0 0 0 0x18000000 0 0x26000>;
|
||||
|
||||
video-codec@2000 {
|
||||
compatible = "mediatek,mtk-vcodec-lat-soc";
|
||||
reg = <0 0x2000 0 0x800>;
|
||||
iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
|
||||
<&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
|
||||
<&topckgen CLK_TOP_UNIVPLL_D4>;
|
||||
clock-names = "sel", "vdec", "lat", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
|
||||
};
|
||||
|
||||
video-codec@10000 {
|
||||
compatible = "mediatek,mtk-vcodec-lat";
|
||||
reg = <0 0x10000 0 0x800>;
|
||||
interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
|
||||
<&topckgen CLK_TOP_UNIVPLL_D4>;
|
||||
clock-names = "sel", "vdec", "lat", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
|
||||
};
|
||||
|
||||
video-codec@25000 {
|
||||
compatible = "mediatek,mtk-vcodec-core";
|
||||
reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */
|
||||
interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
|
||||
<&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC>,
|
||||
<&vdecsys CLK_VDEC_VDEC>,
|
||||
<&vdecsys CLK_VDEC_LAT>,
|
||||
<&topckgen CLK_TOP_UNIVPLL_D4>;
|
||||
clock-names = "sel", "vdec", "lat", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
|
||||
};
|
||||
};
|
||||
|
||||
larb24: larb@1800d000 {
|
||||
compatible = "mediatek,mt8195-smi-larb";
|
||||
reg = <0 0x1800d000 0 0x1000>;
|
||||
@ -3262,5 +3336,185 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vpu0-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
|
||||
|
||||
trips {
|
||||
vpu0_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
vpu0_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vpu1-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
|
||||
|
||||
trips {
|
||||
vpu1_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
vpu1_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu0-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
|
||||
|
||||
trips {
|
||||
gpu0_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
gpu0_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu1-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
|
||||
|
||||
trips {
|
||||
gpu1_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
gpu1_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdec-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
|
||||
|
||||
trips {
|
||||
vdec_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
vdec_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
img-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
|
||||
|
||||
trips {
|
||||
img_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
img_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
infra-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
|
||||
|
||||
trips {
|
||||
infra_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
infra_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cam0-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
|
||||
|
||||
trips {
|
||||
cam0_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cam0_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cam1-thermal {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <250>;
|
||||
thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
|
||||
|
||||
trips {
|
||||
cam1_alert: trip-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cam1_crit: trip-crit {
|
||||
temperature = <100000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
|
||||
#include "mt8365.dtsi"
|
||||
#include "mt6357.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT8365 Open Platform EVK";
|
||||
@ -87,6 +88,49 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
proc-supply = <&mt6357_vproc_reg>;
|
||||
sram-supply = <&mt6357_vsram_proc_reg>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
proc-supply = <&mt6357_vproc_reg>;
|
||||
sram-supply = <&mt6357_vsram_proc_reg>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
proc-supply = <&mt6357_vproc_reg>;
|
||||
sram-supply = <&mt6357_vsram_proc_reg>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
proc-supply = <&mt6357_vproc_reg>;
|
||||
sram-supply = <&mt6357_vsram_proc_reg>;
|
||||
};
|
||||
|
||||
ðernet {
|
||||
pinctrl-0 = <ðernet_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <ð_phy>;
|
||||
phy-mode = "rmii";
|
||||
/*
|
||||
* Ethernet and HDMI (DSI0) are sharing pins.
|
||||
* Only one can be enabled at a time and require the physical switch
|
||||
* SW2101 to be set on LAN position
|
||||
* mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
|
||||
*/
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eth_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
@ -94,7 +138,74 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
hs400-ds-delay = <0x12012>;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
pinctrl-0 = <&mmc0_default_pins>;
|
||||
pinctrl-1 = <&mmc0_uhs_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
vmmc-supply = <&mt6357_vemc_reg>;
|
||||
vqmmc-supply = <&mt6357_vio18_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
|
||||
max-frequency = <200000000>;
|
||||
pinctrl-0 = <&mmc1_default_pins>;
|
||||
pinctrl-1 = <&mmc1_uhs_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-sdr50;
|
||||
vmmc-supply = <&mt6357_vmch_reg>;
|
||||
vqmmc-supply = <&mt6357_vmc_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mt6357_pmic {
|
||||
interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
&pio {
|
||||
ethernet_pins: ethernet-pins {
|
||||
phy_reset_pins {
|
||||
pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
|
||||
};
|
||||
|
||||
rmii_pins {
|
||||
pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
|
||||
<MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
|
||||
<MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
|
||||
<MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
|
||||
<MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
|
||||
<MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
|
||||
<MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
|
||||
<MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
|
||||
<MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
|
||||
<MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
|
||||
<MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
|
||||
<MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
|
||||
<MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
|
||||
<MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
|
||||
<MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
|
||||
<MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys: gpio-keys-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
|
||||
@ -111,6 +222,108 @@
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_default_pins: mmc0-default-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
|
||||
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
|
||||
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
|
||||
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
|
||||
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
|
||||
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
|
||||
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
|
||||
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
|
||||
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_uhs_pins: mmc0-uhs-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
|
||||
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
|
||||
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
|
||||
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
|
||||
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
|
||||
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
|
||||
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
|
||||
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
|
||||
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
ds-pins {
|
||||
pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_default_pins: mmc1-default-pins {
|
||||
cd-pins {
|
||||
pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
|
||||
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
|
||||
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
|
||||
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
|
||||
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_uhs_pins: mmc1-uhs-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
|
||||
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
|
||||
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
|
||||
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
|
||||
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
|
||||
@ -164,6 +377,28 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
pinctrl-0 = <&usb_pins>;
|
||||
pinctrl-names = "default";
|
||||
usb-role-switch;
|
||||
vusb33-supply = <&mt6357_vusb33_reg>;
|
||||
status = "okay";
|
||||
|
||||
connector {
|
||||
compatible = "gpio-usb-b-connector", "usb-b-connector";
|
||||
id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
|
||||
type = "micro";
|
||||
vbus-supply = <&usb_otg_vbus>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host {
|
||||
vusb33-supply = <&mt6357_vusb33_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -20,6 +20,91 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-850000000 {
|
||||
opp-hz = /bits/ 64 <850000000>;
|
||||
opp-microvolt = <650000>;
|
||||
};
|
||||
|
||||
opp-918000000 {
|
||||
opp-hz = /bits/ 64 <918000000>;
|
||||
opp-microvolt = <668750>;
|
||||
};
|
||||
|
||||
opp-987000000 {
|
||||
opp-hz = /bits/ 64 <987000000>;
|
||||
opp-microvolt = <687500>;
|
||||
};
|
||||
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-microvolt = <706250>;
|
||||
};
|
||||
|
||||
opp-1125000000 {
|
||||
opp-hz = /bits/ 64 <1125000000>;
|
||||
opp-microvolt = <725000>;
|
||||
};
|
||||
|
||||
opp-1216000000 {
|
||||
opp-hz = /bits/ 64 <1216000000>;
|
||||
opp-microvolt = <750000>;
|
||||
};
|
||||
|
||||
opp-1308000000 {
|
||||
opp-hz = /bits/ 64 <1308000000>;
|
||||
opp-microvolt = <775000>;
|
||||
};
|
||||
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
||||
opp-1466000000 {
|
||||
opp-hz = /bits/ 64 <1466000000>;
|
||||
opp-microvolt = <825000>;
|
||||
};
|
||||
|
||||
opp-1533000000 {
|
||||
opp-hz = /bits/ 64 <1533000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
|
||||
opp-1633000000 {
|
||||
opp-hz = /bits/ 64 <1633000000>;
|
||||
opp-microvolt = <887500>;
|
||||
};
|
||||
|
||||
opp-1700000000 {
|
||||
opp-hz = /bits/ 64 <1700000000>;
|
||||
opp-microvolt = <912500>;
|
||||
};
|
||||
|
||||
opp-1767000000 {
|
||||
opp-hz = /bits/ 64 <1767000000>;
|
||||
opp-microvolt = <937500>;
|
||||
};
|
||||
|
||||
opp-1834000000 {
|
||||
opp-hz = /bits/ 64 <1834000000>;
|
||||
opp-microvolt = <962500>;
|
||||
};
|
||||
|
||||
opp-1917000000 {
|
||||
opp-hz = /bits/ 64 <1917000000>;
|
||||
opp-microvolt = <993750>;
|
||||
};
|
||||
|
||||
opp-2001000000 {
|
||||
opp-hz = /bits/ 64 <2001000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
@ -43,6 +128,7 @@
|
||||
reg = <0x0>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
@ -50,6 +136,10 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
@ -58,6 +148,7 @@
|
||||
reg = <0x1>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
@ -65,6 +156,10 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate", "armpll";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
@ -73,6 +168,7 @@
|
||||
reg = <0x2>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
@ -80,6 +176,10 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate", "armpll";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
@ -88,6 +188,7 @@
|
||||
reg = <0x3>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
@ -95,6 +196,41 @@
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate", "armpll";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_MCDI: cpu-mcdi {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x00010001>;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <200>;
|
||||
min-residency-us = <1000>;
|
||||
};
|
||||
|
||||
CLUSTER_MCDI: cluster-mcdi {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x01010001>;
|
||||
entry-latency-us = <350>;
|
||||
exit-latency-us = <250>;
|
||||
min-residency-us = <1200>;
|
||||
};
|
||||
|
||||
CLUSTER_DPIDLE: cluster-dpidle {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x01010004>;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <800>;
|
||||
min-residency-us = <3300>;
|
||||
};
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
@ -162,6 +298,12 @@
|
||||
reg = <0 0x10005000 0 0x1000>;
|
||||
};
|
||||
|
||||
watchdog: watchdog@10007000 {
|
||||
compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
|
||||
reg = <0 0x10007000 0 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pio: pinctrl@1000b000 {
|
||||
compatible = "mediatek,mt8365-pinctrl";
|
||||
reg = <0 0x1000b000 0 0x1000>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user