drm/amdgpu:add smu mode1/2 support for aldebaran
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset. Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions. Add mode2_reset_is_support() for smu->ppt_funcs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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4c2e5f513e
commit
5c03e5843e
@ -1261,6 +1261,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
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const u32 array_size);
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bool amdgpu_device_supports_atpx(struct drm_device *dev);
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int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
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bool amdgpu_device_supports_boco(struct drm_device *dev);
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bool amdgpu_device_supports_baco(struct drm_device *dev);
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bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
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@ -4248,6 +4248,45 @@ disabled:
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return false;
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}
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int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
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{
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u32 i;
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int ret = 0;
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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dev_info(adev->dev, "GPU mode1 reset\n");
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/* disable BM */
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pci_clear_master(adev->pdev);
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amdgpu_device_cache_pci_state(adev->pdev);
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if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
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dev_info(adev->dev, "GPU smu mode1 reset\n");
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ret = amdgpu_dpm_mode1_reset(adev);
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} else {
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dev_info(adev->dev, "GPU psp mode1 reset\n");
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ret = psp_gpu_reset(adev);
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}
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if (ret)
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dev_err(adev->dev, "GPU mode1 reset failed\n");
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amdgpu_device_load_pci_state(adev->pdev);
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/* wait for asic to come out of reset */
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for (i = 0; i < adev->usec_timeout; i++) {
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u32 memsize = adev->nbio.funcs->get_memsize(adev);
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if (memsize != 0xffffffff)
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break;
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udelay(1);
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}
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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return ret;
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}
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static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
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struct amdgpu_job *job,
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@ -484,44 +484,6 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
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return -EINVAL;
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}
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static int nv_asic_mode1_reset(struct amdgpu_device *adev)
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{
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u32 i;
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int ret = 0;
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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/* disable BM */
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pci_clear_master(adev->pdev);
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amdgpu_device_cache_pci_state(adev->pdev);
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if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
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dev_info(adev->dev, "GPU smu mode1 reset\n");
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ret = amdgpu_dpm_mode1_reset(adev);
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} else {
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dev_info(adev->dev, "GPU psp mode1 reset\n");
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ret = psp_gpu_reset(adev);
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}
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if (ret)
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dev_err(adev->dev, "GPU mode1 reset failed\n");
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amdgpu_device_load_pci_state(adev->pdev);
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/* wait for asic to come out of reset */
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for (i = 0; i < adev->usec_timeout; i++) {
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u32 memsize = adev->nbio.funcs->get_memsize(adev);
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if (memsize != 0xffffffff)
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break;
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udelay(1);
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}
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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return ret;
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}
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static int nv_asic_mode2_reset(struct amdgpu_device *adev)
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{
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u32 i;
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@ -624,7 +586,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
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break;
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default:
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dev_info(adev->dev, "MODE1 reset\n");
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ret = nv_asic_mode1_reset(adev);
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ret = amdgpu_device_mode1_reset(adev);
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break;
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}
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@ -650,40 +650,6 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
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}
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static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
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{
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u32 i;
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int ret = 0;
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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dev_info(adev->dev, "GPU mode1 reset\n");
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/* disable BM */
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pci_clear_master(adev->pdev);
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amdgpu_device_cache_pci_state(adev->pdev);
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ret = psp_gpu_reset(adev);
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if (ret)
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dev_err(adev->dev, "GPU mode1 reset failed\n");
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amdgpu_device_load_pci_state(adev->pdev);
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/* wait for asic to come out of reset */
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for (i = 0; i < adev->usec_timeout; i++) {
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u32 memsize = adev->nbio.funcs->get_memsize(adev);
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if (memsize != 0xffffffff)
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break;
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udelay(1);
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}
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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return ret;
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}
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static int soc15_asic_baco_reset(struct amdgpu_device *adev)
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{
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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@ -708,13 +674,21 @@ static enum amd_reset_method
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soc15_asic_reset_method(struct amdgpu_device *adev)
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{
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bool baco_reset = false;
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bool connected_to_cpu = false;
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
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connected_to_cpu = true;
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if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
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amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
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amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
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amdgpu_reset_method == AMD_RESET_METHOD_PCI)
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return amdgpu_reset_method;
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amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
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/* If connected to cpu, driver only support mode2 */
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if (connected_to_cpu)
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return AMD_RESET_METHOD_MODE2;
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return amdgpu_reset_method;
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}
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if (amdgpu_reset_method != -1)
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dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
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@ -740,6 +714,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
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if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
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baco_reset = false;
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break;
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case CHIP_ALDEBARAN:
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/*
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* 1.connected to cpu: driver issue mode2 reset
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* 2.discret gpu: driver issue mode1 reset
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*/
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if (connected_to_cpu)
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return AMD_RESET_METHOD_MODE2;
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break;
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default:
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break;
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}
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@ -769,7 +751,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
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return amdgpu_dpm_mode2_reset(adev);
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default:
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dev_info(adev->dev, "MODE1 reset\n");
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return soc15_asic_mode1_reset(adev);
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return amdgpu_device_mode1_reset(adev);
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}
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}
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@ -36,7 +36,7 @@
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// Message Definitions:
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#define PPSMC_MSG_TestMessage 0x1
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#define PPSMC_MSG_GetSmuVersion 0x2
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#define PPSMC_MSG_Mode1Reset 0x3
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#define PPSMC_MSG_GfxDriverReset 0x3
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#define PPSMC_MSG_GetDriverIfVersion 0x4
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#define PPSMC_MSG_spare1 0x5
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#define PPSMC_MSG_spare2 0x6
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@ -70,8 +70,8 @@
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#define PPSMC_MSG_SetPptLimit 0x22
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#define PPSMC_MSG_GetPptLimit 0x23
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#define PPSMC_MSG_PrepareMp1ForUnload 0x24
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#define PPSMC_MSG_PrepareMp1ForReset 0x25
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#define PPSMC_MSG_SoftReset 0x26
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#define PPSMC_MSG_PrepareMp1ForReset 0x25 //retired in 68.07
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#define PPSMC_MSG_SoftReset 0x26 //retired in 68.07
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#define PPSMC_MSG_RunDcBtc 0x27
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#define PPSMC_MSG_DramLogSetDramAddrHigh 0x28
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#define PPSMC_MSG_DramLogSetDramAddrLow 0x29
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@ -92,7 +92,24 @@
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#define PPSMC_MSG_DisableDeterminism 0x3A
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#define PPSMC_MSG_SetUclkDpmMode 0x3B
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#define PPSMC_Message_Count 0x3C
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//STB to dram log
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#define PPSMC_MSG_DumpSTBtoDram 0x3C
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#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x3D
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#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x3E
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#define PPSMC_MSG_STBtoDramLogSetDramSize 0x3F
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#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x40
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#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow 0x41
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#define PPSMC_Message_Count 0x42
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//PPSMC Reset Types
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#define PPSMC_RESET_TYPE_WARM_RESET 0x00
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#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x01 //driver msg argument should be 1 for mode-1
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#define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET 0x02 //and 2 for mode-2
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#define PPSMC_RESET_TYPE_PCIE_LINK_RESET 0x03
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#define PPSMC_RESET_TYPE_BIF_LINK_RESET 0x04
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#define PPSMC_RESET_TYPE_PF0_FLR_RESET 0x05
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typedef enum {
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GFXOFF_ERROR_NO_ERROR,
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@ -1044,6 +1044,10 @@ struct pptable_funcs {
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* @mode1_reset_is_support: Check if GPU supports mode1 reset.
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*/
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bool (*mode1_reset_is_support)(struct smu_context *smu);
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/**
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* @mode2_reset_is_support: Check if GPU supports mode2 reset.
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*/
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bool (*mode2_reset_is_support)(struct smu_context *smu);
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/**
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* @mode1_reset: Perform mode1 reset.
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@ -1279,6 +1283,7 @@ int smu_baco_set_state(void *handle, int state);
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bool smu_mode1_reset_is_support(struct smu_context *smu);
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bool smu_mode2_reset_is_support(struct smu_context *smu);
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int smu_mode1_reset(struct smu_context *smu);
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int smu_mode2_reset(void *handle);
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@ -184,6 +184,7 @@
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__SMU_DUMMY_MAP(GET_UMC_FW_WA), \
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__SMU_DUMMY_MAP(Mode1Reset), \
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__SMU_DUMMY_MAP(RlcPowerNotify), \
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__SMU_DUMMY_MAP(GfxDriverReset), \
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__SMU_DUMMY_MAP(SetHardMinIspiclkByFreq), \
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__SMU_DUMMY_MAP(SetHardMinIspxclkByFreq), \
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__SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \
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@ -220,6 +220,7 @@ int smu_v13_0_baco_enter(struct smu_context *smu);
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int smu_v13_0_baco_exit(struct smu_context *smu);
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int smu_v13_0_mode1_reset(struct smu_context *smu);
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int smu_v13_0_mode2_reset(struct smu_context *smu);
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int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
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uint32_t *min, uint32_t *max);
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@ -1917,6 +1917,9 @@ int smu_set_mp1_state(void *handle,
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msg = SMU_MSG_PrepareMp1ForUnload;
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break;
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case PP_MP1_STATE_RESET:
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/*TODO: since the SMU_MSG_PrepareMp1ForReset is retired in Aldebaran
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* Add handling here forAldebaran.
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*/
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msg = SMU_MSG_PrepareMp1ForReset;
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break;
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case PP_MP1_STATE_NONE:
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@ -2788,6 +2791,23 @@ bool smu_mode1_reset_is_support(struct smu_context *smu)
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return ret;
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}
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bool smu_mode2_reset_is_support(struct smu_context *smu)
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{
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bool ret = false;
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if (!smu->pm_enabled)
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return false;
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mutex_lock(&smu->mutex);
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if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
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ret = smu->ppt_funcs->mode2_reset_is_support(smu);
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mutex_unlock(&smu->mutex);
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return ret;
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}
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int smu_mode1_reset(struct smu_context *smu)
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{
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int ret = 0;
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@ -45,6 +45,7 @@
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#include <linux/pci.h>
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#include "amdgpu_ras.h"
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#include "smu_cmn.h"
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#include "mp/mp_13_0_2_offset.h"
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/*
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* DO NOT use these for err/warn/info/debug messages.
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@ -108,7 +109,7 @@ static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT
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MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
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MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
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MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
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MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
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MSG_MAP(GfxDriverReset, PPSMC_MSG_GfxDriverReset, 0),
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MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0),
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MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
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MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
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@ -1250,6 +1251,31 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
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return sizeof(struct gpu_metrics_v1_0);
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}
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static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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u32 smu_version;
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uint32_t val;
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/**
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* PM FW version support mode1 reset from 68.07
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*/
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smu_cmn_get_smc_version(smu, NULL, &smu_version);
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if ((smu_version < 0x00440700))
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return false;
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/**
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* mode1 reset relies on PSP, so we should check if
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* PSP is alive.
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*/
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val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
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return val != 0x0;
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}
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static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
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{
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return true;
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}
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static const struct pptable_funcs aldebaran_ppt_funcs = {
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/* init dpm */
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.get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
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@ -1305,6 +1331,10 @@ static const struct pptable_funcs aldebaran_ppt_funcs = {
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.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
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.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
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.get_gpu_metrics = aldebaran_get_gpu_metrics,
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.mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
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.mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
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.mode1_reset = smu_v13_0_mode1_reset,
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.mode2_reset = smu_v13_0_mode2_reset,
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};
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void aldebaran_set_ppt_funcs(struct smu_context *smu)
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@ -1349,15 +1349,39 @@ int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
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int smu_v13_0_mode1_reset(struct smu_context *smu)
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{
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u32 smu_version;
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int ret = 0;
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/*
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* PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
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*/
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smu_cmn_get_smc_version(smu, NULL, &smu_version);
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if (smu_version < 0x00440700)
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
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else
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL);
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
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if (!ret)
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msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
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return ret;
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}
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int smu_v13_0_mode2_reset(struct smu_context *smu)
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{
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u32 smu_version;
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int ret = 0;
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struct amdgpu_device *adev = smu->adev;
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smu_cmn_get_smc_version(smu, NULL, &smu_version);
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if (smu_version >= 0x00440700)
|
||||
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
|
||||
else
|
||||
dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", smu_version);
|
||||
/*TODO: mode2 reset wait time should be shorter, will modify it later*/
|
||||
if (!ret)
|
||||
msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
|
||||
uint32_t *min, uint32_t *max)
|
||||
{
|
||||
|
Loading…
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Reference in New Issue
Block a user