RDMA/rxe: Extend rxe packet format to support atomic write
Extend rxe_wr_opcode_info[] and rxe_opcode[] for new atomic write opcode. Link: https://lore.kernel.org/r/1669905432-14-5-git-send-email-yangx.jy@fujitsu.com Signed-off-by: Xiao Yang <yangx.jy@fujitsu.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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@ -101,6 +101,12 @@ struct rxe_wr_opcode_info rxe_wr_opcode_info[] = {
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[IB_QPT_UC] = WR_LOCAL_OP_MASK,
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},
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},
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[IB_WR_ATOMIC_WRITE] = {
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.name = "IB_WR_ATOMIC_WRITE",
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.mask = {
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[IB_QPT_RC] = WR_ATOMIC_WRITE_MASK,
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},
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},
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};
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struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE] = {
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@ -378,6 +384,18 @@ struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE] = {
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RXE_IETH_BYTES,
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}
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},
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[IB_OPCODE_RC_ATOMIC_WRITE] = {
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.name = "IB_OPCODE_RC_ATOMIC_WRITE",
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.mask = RXE_RETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK |
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RXE_ATOMIC_WRITE_MASK | RXE_START_MASK |
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RXE_END_MASK,
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.length = RXE_BTH_BYTES + RXE_RETH_BYTES,
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.offset = {
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[RXE_BTH] = 0,
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[RXE_RETH] = RXE_BTH_BYTES,
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[RXE_PAYLOAD] = RXE_BTH_BYTES + RXE_RETH_BYTES,
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}
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},
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/* UC */
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[IB_OPCODE_UC_SEND_FIRST] = {
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@ -20,6 +20,7 @@ enum rxe_wr_mask {
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WR_READ_MASK = BIT(3),
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WR_WRITE_MASK = BIT(4),
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WR_LOCAL_OP_MASK = BIT(5),
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WR_ATOMIC_WRITE_MASK = BIT(7),
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WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK,
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WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK,
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@ -81,6 +82,8 @@ enum rxe_hdr_mask {
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RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12),
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RXE_ATOMIC_WRITE_MASK = BIT(NUM_HDR_TYPES + 14),
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RXE_READ_OR_ATOMIC_MASK = (RXE_READ_MASK | RXE_ATOMIC_MASK),
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RXE_WRITE_OR_SEND_MASK = (RXE_WRITE_MASK | RXE_SEND_MASK),
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RXE_READ_OR_WRITE_MASK = (RXE_READ_MASK | RXE_WRITE_MASK),
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