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imx-drm limit fixes

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Fix IPU IC downscaler to its hardware limitation of 4:1 and the
 IPU DI pixel clock divider integer part to 8-bit.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJVGnyFAAoJEFDCiBxwnmDrP9IQAI+hF9AwH645S7VS2aWJdepn
 It+LSh2lQ0Mn8Q2pQYDuoJAoM2u98H04270lhL5JfSc1uqdiud6J+hzSG/0D8fqu
 6ZDMV+yen3edo3B3HXtmAbglv6DGEht5HjEcjKIJ14vV0l+q6AdLPwKVbZkw3hl2
 LMeexTDx/rMnWizhiXrAGaYmOTYawXOWM/kj1NbQYCBQfVScsJcmrd11NC6xE5ak
 Mvpv4wtwQ5/g/XwDeBZLRF6+WL9dvRdj0gId6JMisCG7mMOXZxHAKArarWqY7FUE
 sRtMkvnBmgrZhmkXcBXWN3DgdSC1kSWa6CZqHWDdVDnmcU0cozKsnrAoZdGLfhS9
 +ryml/poUA9IEqZTtb/XuzY+gYEyXX5PoLoqdcWXgiEuFgWgdM1CilrmJl+IxyIj
 A5/NaA9SUHVqGAF1+5b4nTjFYCl6UuZnLlx+ov3MfK1C4w9c711GUUt24PBv9KFy
 eYVOswg+cqWkXfeYiLFAv2BoB8pkhDCLwhySRhCjHYJq9NfTgViwCLCYJ59RTQPs
 auz6d9wN19D4rE1eagV4LeTPDZVuoTYcE9RxHGhl32fO1ISq0u0L9xRq5X63CF6k
 1LajiyGdD9aJbuAgaywGqmRuGiCasOdgqp6KV68cLRuQ86Dd6R9a8vQ5tw/cWERD
 td2rf0B0zduI34/S98oS
 =1E75
 -----END PGP SIGNATURE-----

Merge tag 'imx-drm-fixes-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next

imx-drm limit fixes

Fix IPU IC downscaler to its hardware limitation of 4:1 and the
IPU DI pixel clock divider integer part to 8-bit.

* tag 'imx-drm-fixes-2015-03-31' of git://git.pengutronix.de/git/pza/linux:
  gpu: ipu-v3: turns out the IPU can only downsize 4:1
  gpu: ipu-v3: limit pixel clock divider to 8-bits
  drm/radeon: programm the VCE fw BAR as well
  drm/radeon: always dump the ring content if it's available
  radeon: Do not directly dereference pointers to BIOS area.
  drm/radeon/dpm: fix 120hz handling harder
This commit is contained in:
Dave Airlie 2015-04-08 11:19:24 +10:00
commit 5c7f0c2795
8 changed files with 35 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/radeon/cikd.h
View File

@ -2131,6 +2131,7 @@
#define VCE_UENC_REG_CLOCK_GATING 0x207c0
#define VCE_SYS_INT_EN 0x21300
# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
#define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c
#define VCE_LMI_CTRL2 0x21474
#define VCE_LMI_CTRL 0x21498
#define VCE_LMI_VM_CTRL 0x214a0

1
drivers/gpu/drm/radeon/radeon.h
View File

@ -1567,6 +1567,7 @@ struct radeon_dpm {
int new_active_crtc_count;
u32 current_active_crtcs;
int current_active_crtc_count;
bool single_display;
struct radeon_dpm_dynamic_state dyn_state;
struct radeon_dpm_fan fan;
u32 tdp_limit;

10
drivers/gpu/drm/radeon/radeon_bios.c
View File

@ -76,7 +76,7 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
static bool radeon_read_bios(struct radeon_device *rdev)
{
uint8_t __iomem *bios;
uint8_t __iomem *bios, val1, val2;
size_t size;
rdev->bios = NULL;
@ -86,15 +86,19 @@ static bool radeon_read_bios(struct radeon_device *rdev)
return false;
}
if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
val1 = readb(&bios[0]);
val2 = readb(&bios[1]);
if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
pci_unmap_rom(rdev->pdev, bios);
return false;
}
rdev->bios = kmemdup(bios, size, GFP_KERNEL);
rdev->bios = kzalloc(size, GFP_KERNEL);
if (rdev->bios == NULL) {
pci_unmap_rom(rdev->pdev, bios);
return false;
}
memcpy_fromio(rdev->bios, bios, size);
pci_unmap_rom(rdev->pdev, bios);
return true;
}

22
drivers/gpu/drm/radeon/radeon_pm.c
View File

@ -837,12 +837,8 @@ static void radeon_dpm_thermal_work_handler(struct work_struct *work)
radeon_pm_compute_clocks(rdev);
}
static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
enum radeon_pm_state_type dpm_state)
static bool radeon_dpm_single_display(struct radeon_device *rdev)
{
int i;
struct radeon_ps *ps;
u32 ui_class;
bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
true : false;
@ -858,6 +854,17 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
single_display = false;
return single_display;
}
static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
enum radeon_pm_state_type dpm_state)
{
int i;
struct radeon_ps *ps;
u32 ui_class;
bool single_display = radeon_dpm_single_display(rdev);
/* certain older asics have a separare 3D performance state,
* so try that first if the user selected performance
*/
@ -983,6 +990,7 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
struct radeon_ps *ps;
enum radeon_pm_state_type dpm_state;
int ret;
bool single_display = radeon_dpm_single_display(rdev);
/* if dpm init failed */
if (!rdev->pm.dpm_enabled)
@ -1007,6 +1015,9 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
/* vce just modifies an existing state so force a change */
if (ps->vce_active != rdev->pm.dpm.vce_active)
goto force;
/* user has made a display change (such as timing) */
if (rdev->pm.dpm.single_display != single_display)
goto force;
if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
/* for pre-BTC and APUs if the num crtcs changed but state is the same,
* all we need to do is update the display configuration.
@ -1069,6 +1080,7 @@ force:
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
rdev->pm.dpm.single_display = single_display;
/* wait for the rings to drain */
for (i = 0; i < RADEON_NUM_RINGS; i++) {

2
drivers/gpu/drm/radeon/radeon_ring.c
View File

@ -495,7 +495,7 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
seq_printf(m, "%u dwords in ring\n", count);
if (!ring->ready)
if (!ring->ring)
return 0;
/* print 8 dw before current rptr as often it's the last executed

3
drivers/gpu/drm/radeon/vce_v2_0.c
View File

@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev)
WREG32(VCE_LMI_SWAP_CNTL1, 0);
WREG32(VCE_LMI_VM_CTRL, 0);
WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
addr &= 0xff;
size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
WREG32(VCE_VCPU_CACHE_SIZE0, size);

9
drivers/gpu/ipu-v3/ipu-di.c
View File

@ -441,8 +441,7 @@ static void ipu_di_config_clock(struct ipu_di *di,
in_rate = clk_get_rate(clk);
div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
if (div == 0)
div = 1;
div = clamp(div, 1U, 255U);
clkgen0 = div << 4;
}
@ -459,8 +458,7 @@ static void ipu_di_config_clock(struct ipu_di *di,
clkrate = clk_get_rate(di->clk_ipu);
div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);
if (div == 0)
div = 1;
div = clamp(div, 1U, 255U);
rate = clkrate / div;
error = rate / (sig->mode.pixelclock / 1000);
@ -483,8 +481,7 @@ static void ipu_di_config_clock(struct ipu_di *di,
in_rate = clk_get_rate(clk);
div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
if (div == 0)
div = 1;
div = clamp(div, 1U, 255U);
clkgen0 = div << 4;
}

4
drivers/gpu/ipu-v3/ipu-ic.c
View File

@ -297,8 +297,8 @@ static int calc_resize_coeffs(struct ipu_ic *ic,
return -EINVAL;
}
/* Cannot downsize more than 8:1 */
if ((out_size << 3) < in_size) {
/* Cannot downsize more than 4:1 */
if ((out_size << 2) < in_size) {
dev_err(ipu->dev, "Unsupported downsize\n");
return -EINVAL;
}