perf vendor events arm64: Add V1 metrics using Arm telemetry repo
Metrics for V1 weren't previously included in the Perf Jsons, so add them using the telemetry source [1]. After generation any parts identical to the default metrics in sbsa.json were manually removed. [1]: https://gitlab.arm.com/telemetry-solution/telemetry-solution/-/blob/main/data/pmu/cpu/neoverse/neoverse-v1.json Signed-off-by: James Clark <james.clark@arm.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Nick Forrington <nick.forrington@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230831161618.134738-3-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
James Clark
Arnaldo Carvalho de Melo
parent
a484e64580
commit
5cdb51baf3
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tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/metrics.json
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tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/metrics.json
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[
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{
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"ArchStdEvent": "backend_bound"
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},
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{
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"MetricName": "backend_stalled_cycles",
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"MetricExpr": "((STALL_BACKEND / CPU_CYCLES) * 100)",
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"BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the backend unit of the processor.",
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"MetricGroup": "Cycle_Accounting",
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"ScaleUnit": "1percent of cycles"
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},
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{
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"ArchStdEvent": "bad_speculation",
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"MetricExpr": "(100 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (STALL_SLOT / (CPU_CYCLES * 8)))) + ((BR_MIS_PRED * 4) / CPU_CYCLES)))"
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},
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{
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"MetricName": "branch_misprediction_ratio",
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"MetricExpr": "(BR_MIS_PRED_RETIRED / BR_RETIRED)",
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"BriefDescription": "This metric measures the ratio of branches mispredicted to the total number of branches architecturally executed. This gives an indication of the effectiveness of the branch prediction unit.",
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"MetricGroup": "Miss_Ratio;Branch_Effectiveness",
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"ScaleUnit": "1per branch"
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},
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{
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"MetricName": "branch_mpki",
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"MetricExpr": "((BR_MIS_PRED_RETIRED / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of branch mispredictions per thousand instructions executed.",
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"MetricGroup": "MPKI;Branch_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "branch_percentage",
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"MetricExpr": "(((BR_IMMED_SPEC + BR_INDIRECT_SPEC) / INST_SPEC) * 100)",
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"BriefDescription": "This metric measures branch operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "crypto_percentage",
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"MetricExpr": "((CRYPTO_SPEC / INST_SPEC) * 100)",
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"BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "dtlb_mpki",
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"MetricExpr": "((DTLB_WALK / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions executed.",
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"MetricGroup": "MPKI;DTLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "dtlb_walk_ratio",
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"MetricExpr": "(DTLB_WALK / L1D_TLB)",
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"BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.",
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"MetricGroup": "Miss_Ratio;DTLB_Effectiveness",
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"ScaleUnit": "1per TLB access"
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},
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{
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"ArchStdEvent": "frontend_bound",
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"MetricExpr": "(100 * ((STALL_SLOT_FRONTEND / (CPU_CYCLES * 8)) - ((BR_MIS_PRED * 4) / CPU_CYCLES)))"
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},
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{
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"MetricName": "frontend_stalled_cycles",
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"MetricExpr": "((STALL_FRONTEND / CPU_CYCLES) * 100)",
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"BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the frontend unit of the processor.",
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"MetricGroup": "Cycle_Accounting",
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"ScaleUnit": "1percent of cycles"
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},
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{
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"MetricName": "integer_dp_percentage",
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"MetricExpr": "((DP_SPEC / INST_SPEC) * 100)",
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"BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "ipc",
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"MetricExpr": "(INST_RETIRED / CPU_CYCLES)",
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"BriefDescription": "This metric measures the number of instructions retired per cycle.",
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"MetricGroup": "General",
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"ScaleUnit": "1per cycle"
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},
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{
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"MetricName": "itlb_mpki",
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"MetricExpr": "((ITLB_WALK / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instructions executed.",
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"MetricGroup": "MPKI;ITLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "itlb_walk_ratio",
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"MetricExpr": "(ITLB_WALK / L1I_TLB)",
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"BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.",
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"MetricGroup": "Miss_Ratio;ITLB_Effectiveness",
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"ScaleUnit": "1per TLB access"
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},
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{
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"MetricName": "l1d_cache_miss_ratio",
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"MetricExpr": "(L1D_CACHE_REFILL / L1D_CACHE)",
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"BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.",
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"MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness",
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"ScaleUnit": "1per cache access"
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},
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{
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"MetricName": "l1d_cache_mpki",
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"MetricExpr": "((L1D_CACHE_REFILL / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;L1D_Cache_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l1d_tlb_miss_ratio",
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"MetricExpr": "(L1D_TLB_REFILL / L1D_TLB)",
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"BriefDescription": "This metric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indication of the effectiveness of the level 1 data TLB.",
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"MetricGroup": "Miss_Ratio;DTLB_Effectiveness",
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"ScaleUnit": "1per TLB access"
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},
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{
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"MetricName": "l1d_tlb_mpki",
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"MetricExpr": "((L1D_TLB_REFILL / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;DTLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l1i_cache_miss_ratio",
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"MetricExpr": "(L1I_CACHE_REFILL / L1I_CACHE)",
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"BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.",
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"MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness",
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"ScaleUnit": "1per cache access"
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},
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{
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"MetricName": "l1i_cache_mpki",
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"MetricExpr": "((L1I_CACHE_REFILL / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;L1I_Cache_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l1i_tlb_miss_ratio",
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"MetricExpr": "(L1I_TLB_REFILL / L1I_TLB)",
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"BriefDescription": "This metric measures the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indication of the effectiveness of the level 1 instruction TLB.",
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"MetricGroup": "Miss_Ratio;ITLB_Effectiveness",
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"ScaleUnit": "1per TLB access"
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},
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{
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"MetricName": "l1i_tlb_mpki",
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"MetricExpr": "((L1I_TLB_REFILL / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;ITLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l2_cache_miss_ratio",
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"MetricExpr": "(L2D_CACHE_REFILL / L2D_CACHE)",
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"BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.",
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"MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness",
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"ScaleUnit": "1per cache access"
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},
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{
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"MetricName": "l2_cache_mpki",
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"MetricExpr": "((L2D_CACHE_REFILL / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per thousand instructions executed. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.",
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"MetricGroup": "MPKI;L2_Cache_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l2_tlb_miss_ratio",
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"MetricExpr": "(L2D_TLB_REFILL / L2D_TLB)",
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"BriefDescription": "This metric measures the ratio of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. This gives an indication of the effectiveness of the level 2 TLB.",
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"MetricGroup": "Miss_Ratio;ITLB_Effectiveness;DTLB_Effectiveness",
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"ScaleUnit": "1per TLB access"
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},
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{
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"MetricName": "l2_tlb_mpki",
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"MetricExpr": "((L2D_TLB_REFILL / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;ITLB_Effectiveness;DTLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "ll_cache_read_hit_ratio",
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"MetricExpr": "((LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD)",
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"BriefDescription": "This metric measures the ratio of last level cache read accesses hit in the cache to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.",
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"MetricGroup": "LL_Cache_Effectiveness",
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"ScaleUnit": "1per cache access"
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},
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{
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"MetricName": "ll_cache_read_miss_ratio",
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"MetricExpr": "(LL_CACHE_MISS_RD / LL_CACHE_RD)",
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"BriefDescription": "This metric measures the ratio of last level cache read accesses missed to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.",
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"MetricGroup": "Miss_Ratio;LL_Cache_Effectiveness",
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"ScaleUnit": "1per cache access"
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},
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{
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"MetricName": "ll_cache_read_mpki",
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"MetricExpr": "((LL_CACHE_MISS_RD / INST_RETIRED) * 1000)",
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"BriefDescription": "This metric measures the number of last level cache read accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;LL_Cache_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "load_percentage",
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"MetricExpr": "((LD_SPEC / INST_SPEC) * 100)",
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"BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"ArchStdEvent": "retiring"
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},
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{
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"MetricName": "scalar_fp_percentage",
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"MetricExpr": "((VFP_SPEC / INST_SPEC) * 100)",
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"BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "simd_percentage",
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"MetricExpr": "((ASE_SPEC / INST_SPEC) * 100)",
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"BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "store_percentage",
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"MetricExpr": "((ST_SPEC / INST_SPEC) * 100)",
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"BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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}
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]
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