drm/msm/dsi: push provided clocks handling into a generic code
All MSM DSI PHYs provide two clocks: byte and pixel ones. Register/unregister provided clocks from the generic place, removing boilerplate code from all MSM DSI PHY drivers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor Link: https://lore.kernel.org/r/20210331105735.3690009-11-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Dmitry Baryshkov
Rob Clark
parent
95b814e4f6
commit
5d13459650
@ -96,19 +96,12 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi);
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struct msm_dsi_pll;
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#ifdef CONFIG_DRM_MSM_DSI_PLL
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void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
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int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
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struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
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void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
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int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
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#else
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static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
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{
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}
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static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
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struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
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{
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return -ENODEV;
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}
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static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll)
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{
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}
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@ -144,7 +137,7 @@ struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);
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int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer);
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void msm_dsi_host_unregister(struct mipi_dsi_host *host);
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int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
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struct msm_dsi_pll *src_pll);
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struct msm_dsi_phy *src_phy);
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void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
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void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
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struct msm_dsi_phy_clk_request *clk_req,
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@ -196,6 +189,8 @@ void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
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struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
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void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
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enum msm_dsi_phy_usecase uc);
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int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
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struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
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#endif /* __DSI_CONNECTOR_H__ */
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@ -2224,13 +2224,13 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
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}
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int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
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struct msm_dsi_pll *src_pll)
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struct msm_dsi_phy *src_phy)
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{
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struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
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struct clk *byte_clk_provider, *pixel_clk_provider;
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int ret;
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ret = msm_dsi_pll_get_clk_provider(src_pll,
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ret = msm_dsi_phy_get_clk_provider(src_phy,
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&byte_clk_provider, &pixel_clk_provider);
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if (ret) {
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pr_info("%s: can't get provider from pll, don't set parent\n",
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@ -70,7 +70,6 @@ static int dsi_mgr_setup_components(int id)
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struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id);
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struct msm_dsi *clk_master_dsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
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struct msm_dsi *clk_slave_dsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
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struct msm_dsi_pll *src_pll;
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int ret;
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if (!IS_DUAL_DSI()) {
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@ -79,10 +78,7 @@ static int dsi_mgr_setup_components(int id)
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return ret;
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msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE);
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src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
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if (IS_ERR(src_pll))
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return PTR_ERR(src_pll);
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ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
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ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy);
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} else if (!other_dsi) {
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ret = 0;
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} else {
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@ -109,13 +105,10 @@ static int dsi_mgr_setup_components(int id)
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MSM_DSI_PHY_MASTER);
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msm_dsi_phy_set_usecase(clk_slave_dsi->phy,
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MSM_DSI_PHY_SLAVE);
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src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy);
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if (IS_ERR(src_pll))
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return PTR_ERR(src_pll);
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ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
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ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy);
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if (ret)
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return ret;
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ret = msm_dsi_host_set_src_pll(other_dsi->host, src_pll);
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ret = msm_dsi_host_set_src_pll(other_dsi->host, clk_master_dsi->phy);
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}
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return ret;
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@ -3,6 +3,7 @@
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "dsi_phy.h"
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@ -652,6 +653,14 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
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if (!match)
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return -ENODEV;
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phy->provided_clocks = devm_kzalloc(dev,
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struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS),
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GFP_KERNEL);
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if (!phy->provided_clocks)
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return -ENOMEM;
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phy->provided_clocks->num = NUM_PROVIDED_CLKS;
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phy->cfg = match->data;
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phy->pdev = pdev;
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@ -719,6 +728,13 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
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}
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}
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ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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phy->provided_clocks);
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if (ret) {
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DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n", __func__, ret);
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goto fail;
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}
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dsi_phy_disable_resource(phy);
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platform_set_drvdata(pdev, phy);
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@ -726,6 +742,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
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return 0;
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fail:
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if (phy->pll) {
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of_clk_del_provider(dev->of_node);
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msm_dsi_pll_destroy(phy->pll);
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phy->pll = NULL;
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}
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return ret;
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}
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@ -734,6 +756,7 @@ static int dsi_phy_driver_remove(struct platform_device *pdev)
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struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
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if (phy && phy->pll) {
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of_clk_del_provider(pdev->dev.of_node);
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msm_dsi_pll_destroy(phy->pll);
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phy->pll = NULL;
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}
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@ -851,3 +874,14 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
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if (phy)
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phy->usecase = uc;
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}
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int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
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struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
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{
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if (byte_clk_provider)
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*byte_clk_provider = phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk;
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if (pixel_clk_provider)
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*pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk;
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return -EINVAL;
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}
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@ -23,9 +23,6 @@ struct msm_dsi_phy_ops {
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struct msm_dsi_pll_ops {
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int (*enable_seq)(struct msm_dsi_pll *pll);
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void (*disable_seq)(struct msm_dsi_pll *pll);
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int (*get_provider)(struct msm_dsi_pll *pll,
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struct clk **byte_clk_provider,
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struct clk **pixel_clk_provider);
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void (*destroy)(struct msm_dsi_pll *pll);
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void (*save_state)(struct msm_dsi_pll *pll);
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int (*restore_state)(struct msm_dsi_pll *pll);
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@ -87,6 +84,10 @@ struct msm_dsi_dphy_timing {
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u8 hs_halfbyte_en_ckln;
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};
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#define DSI_BYTE_PLL_CLK 0
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#define DSI_PIXEL_PLL_CLK 1
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#define NUM_PROVIDED_CLKS 2
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struct msm_dsi_phy {
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struct platform_device *pdev;
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void __iomem *base;
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@ -104,6 +105,8 @@ struct msm_dsi_phy {
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bool regulator_ldo_mode;
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struct msm_dsi_pll *pll;
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struct clk_hw_onecell_data *provided_clocks;
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};
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/*
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@ -36,10 +36,6 @@
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* dsi0_pll_post_out_div_clk
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*/
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#define DSI_BYTE_PLL_CLK 0
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#define DSI_PIXEL_PLL_CLK 1
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#define NUM_PROVIDED_CLKS 2
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#define VCO_REF_CLK_RATE 19200000
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struct dsi_pll_regs {
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@ -116,9 +112,6 @@ struct dsi_pll_10nm {
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struct clk_hw *pclk_mux_hw;
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struct clk_hw *out_dsiclk_hw;
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/* clock-provider: */
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struct clk_hw_onecell_data *hw_data;
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struct pll_10nm_cached_state cached_state;
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enum msm_dsi_phy_usecase uc;
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@ -621,30 +614,11 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
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return 0;
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}
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static int dsi_pll_10nm_get_provider(struct msm_dsi_pll *pll,
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struct clk **byte_clk_provider,
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struct clk **pixel_clk_provider)
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{
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struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
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struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data;
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DBG("DSI PLL%d", pll_10nm->id);
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if (byte_clk_provider)
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*byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
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if (pixel_clk_provider)
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*pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
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return 0;
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}
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static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
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{
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struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
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struct device *dev = &pll_10nm->pdev->dev;
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DBG("DSI PLL%d", pll_10nm->id);
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of_clk_del_provider(dev->of_node);
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clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
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clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
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@ -662,7 +636,7 @@ static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
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* state to follow the master PLL's divider/mux state. Therefore, we don't
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* require special clock ops that also configure the slave PLL registers
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*/
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static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
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static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **provided_clocks)
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{
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char clk_name[32], parent[32], vco_name[32];
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char parent2[32], parent3[32], parent4[32];
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@ -674,18 +648,11 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
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.ops = &clk_ops_dsi_pll_10nm_vco,
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};
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struct device *dev = &pll_10nm->pdev->dev;
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struct clk_hw_onecell_data *hw_data;
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struct clk_hw *hw;
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int ret;
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DBG("DSI%d", pll_10nm->id);
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hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
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NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
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GFP_KERNEL);
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if (!hw_data)
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return -ENOMEM;
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snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
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pll_10nm->base.clk_hw.init = &vco_init;
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@ -737,7 +704,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
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}
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pll_10nm->byte_clk_hw = hw;
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hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
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provided_clocks[DSI_BYTE_PLL_CLK] = hw;
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snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
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snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
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@ -797,22 +764,10 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
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}
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pll_10nm->out_dsiclk_hw = hw;
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hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
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hw_data->num = NUM_PROVIDED_CLKS;
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pll_10nm->hw_data = hw_data;
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ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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pll_10nm->hw_data);
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if (ret) {
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DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
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goto err_dsiclk_hw;
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}
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provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
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return 0;
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err_dsiclk_hw:
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clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
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err_pclk_mux_hw:
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clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
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err_post_out_div_clk_hw:
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@ -868,7 +823,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
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pll_10nm->vco_delay = 1;
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ret = pll_10nm_register(pll_10nm);
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ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
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if (ret) {
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DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
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return ret;
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@ -1105,7 +1060,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
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.pll_init = dsi_pll_10nm_init,
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},
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.pll_ops = {
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.get_provider = dsi_pll_10nm_get_provider,
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.destroy = dsi_pll_10nm_destroy,
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.save_state = dsi_pll_10nm_save_state,
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.restore_state = dsi_pll_10nm_restore_state,
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@ -1131,7 +1085,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
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.pll_init = dsi_pll_10nm_init,
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},
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.pll_ops = {
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.get_provider = dsi_pll_10nm_get_provider,
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.destroy = dsi_pll_10nm_destroy,
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.save_state = dsi_pll_10nm_save_state,
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.restore_state = dsi_pll_10nm_restore_state,
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@ -34,15 +34,10 @@
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#define POLL_MAX_READS 15
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#define POLL_TIMEOUT_US 1000
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#define NUM_PROVIDED_CLKS 2
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#define VCO_REF_CLK_RATE 19200000
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#define VCO_MIN_RATE 1300000000UL
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#define VCO_MAX_RATE 2600000000UL
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#define DSI_BYTE_PLL_CLK 0
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#define DSI_PIXEL_PLL_CLK 1
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#define DSI_PLL_DEFAULT_VCO_POSTDIV 1
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struct dsi_pll_input {
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@ -142,9 +137,6 @@ struct dsi_pll_14nm {
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struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
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u32 num_hws;
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/* clock-provider: */
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struct clk_hw_onecell_data *hw_data;
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struct pll_14nm_cached_state cached_state;
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enum msm_dsi_phy_usecase uc;
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@ -880,29 +872,11 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
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return 0;
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}
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static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll,
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struct clk **byte_clk_provider,
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struct clk **pixel_clk_provider)
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{
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struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
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struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data;
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if (byte_clk_provider)
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*byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
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if (pixel_clk_provider)
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*pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
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return 0;
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}
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static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)
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{
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struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
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struct platform_device *pdev = pll_14nm->pdev;
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int num_hws = pll_14nm->num_hws;
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|
||||
of_clk_del_provider(pdev->dev.of_node);
|
||||
|
||||
while (num_hws--)
|
||||
clk_hw_unregister(pll_14nm->hws[num_hws]);
|
||||
}
|
||||
@ -943,7 +917,7 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
|
||||
return &pll_postdiv->hw;
|
||||
}
|
||||
|
||||
static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
|
||||
static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks)
|
||||
{
|
||||
char clk_name[32], parent[32], vco_name[32];
|
||||
struct clk_init_data vco_init = {
|
||||
@ -955,19 +929,12 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
|
||||
};
|
||||
struct device *dev = &pll_14nm->pdev->dev;
|
||||
struct clk_hw **hws = pll_14nm->hws;
|
||||
struct clk_hw_onecell_data *hw_data;
|
||||
struct clk_hw *hw;
|
||||
int num = 0;
|
||||
int ret;
|
||||
|
||||
DBG("DSI%d", pll_14nm->id);
|
||||
|
||||
hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
|
||||
NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
|
||||
GFP_KERNEL);
|
||||
if (!hw_data)
|
||||
return -ENOMEM;
|
||||
|
||||
snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
|
||||
pll_14nm->base.clk_hw.init = &vco_init;
|
||||
|
||||
@ -998,7 +965,7 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
|
||||
return PTR_ERR(hw);
|
||||
|
||||
hws[num++] = hw;
|
||||
hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
|
||||
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
|
||||
|
||||
snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
|
||||
snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
|
||||
@ -1025,20 +992,10 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
|
||||
return PTR_ERR(hw);
|
||||
|
||||
hws[num++] = hw;
|
||||
hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
|
||||
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
|
||||
|
||||
pll_14nm->num_hws = num;
|
||||
|
||||
hw_data->num = NUM_PROVIDED_CLKS;
|
||||
pll_14nm->hw_data = hw_data;
|
||||
|
||||
ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
|
||||
pll_14nm->hw_data);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1082,7 +1039,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
|
||||
|
||||
pll_14nm->vco_delay = 1;
|
||||
|
||||
ret = pll_14nm_register(pll_14nm);
|
||||
ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
|
||||
return ret;
|
||||
@ -1227,7 +1184,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
|
||||
.pll_init = dsi_pll_14nm_init,
|
||||
},
|
||||
.pll_ops = {
|
||||
.get_provider = dsi_pll_14nm_get_provider,
|
||||
.destroy = dsi_pll_14nm_destroy,
|
||||
.save_state = dsi_pll_14nm_save_state,
|
||||
.restore_state = dsi_pll_14nm_restore_state,
|
||||
@ -1255,7 +1211,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
|
||||
.pll_init = dsi_pll_14nm_init,
|
||||
},
|
||||
.pll_ops = {
|
||||
.get_provider = dsi_pll_14nm_get_provider,
|
||||
.destroy = dsi_pll_14nm_destroy,
|
||||
.save_state = dsi_pll_14nm_save_state,
|
||||
.restore_state = dsi_pll_14nm_restore_state,
|
||||
|
||||
@ -31,15 +31,10 @@
|
||||
#define POLL_MAX_READS 10
|
||||
#define POLL_TIMEOUT_US 50
|
||||
|
||||
#define NUM_PROVIDED_CLKS 2
|
||||
|
||||
#define VCO_REF_CLK_RATE 19200000
|
||||
#define VCO_MIN_RATE 350000000
|
||||
#define VCO_MAX_RATE 750000000
|
||||
|
||||
#define DSI_BYTE_PLL_CLK 0
|
||||
#define DSI_PIXEL_PLL_CLK 1
|
||||
|
||||
/* v2.0.0 28nm LP implementation */
|
||||
#define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0)
|
||||
|
||||
@ -83,10 +78,6 @@ struct dsi_pll_28nm {
|
||||
struct clk *clks[NUM_DSI_CLOCKS_MAX];
|
||||
u32 num_clks;
|
||||
|
||||
/* clock-provider: */
|
||||
struct clk *provided_clks[NUM_PROVIDED_CLKS];
|
||||
struct clk_onecell_data clk_data;
|
||||
|
||||
struct pll_28nm_cached_state cached_state;
|
||||
};
|
||||
|
||||
@ -495,38 +486,16 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
|
||||
struct clk **byte_clk_provider,
|
||||
struct clk **pixel_clk_provider)
|
||||
{
|
||||
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
||||
|
||||
if (byte_clk_provider)
|
||||
*byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
|
||||
if (pixel_clk_provider)
|
||||
*pixel_clk_provider =
|
||||
pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
|
||||
{
|
||||
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
||||
int i;
|
||||
|
||||
msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
|
||||
pll_28nm->clks, pll_28nm->num_clks);
|
||||
|
||||
for (i = 0; i < NUM_PROVIDED_CLKS; i++)
|
||||
pll_28nm->provided_clks[i] = NULL;
|
||||
msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks);
|
||||
|
||||
pll_28nm->num_clks = 0;
|
||||
pll_28nm->clk_data.clks = NULL;
|
||||
pll_28nm->clk_data.clk_num = 0;
|
||||
}
|
||||
|
||||
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
||||
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)
|
||||
{
|
||||
char clk_name[32], parent1[32], parent2[32], vco_name[32];
|
||||
struct clk_init_data vco_init = {
|
||||
@ -538,9 +507,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
||||
};
|
||||
struct device *dev = &pll_28nm->pdev->dev;
|
||||
struct clk **clks = pll_28nm->clks;
|
||||
struct clk **provided_clks = pll_28nm->provided_clks;
|
||||
int num = 0;
|
||||
int ret;
|
||||
|
||||
DBG("%d", pll_28nm->id);
|
||||
|
||||
@ -564,11 +531,11 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
||||
|
||||
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
|
||||
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
|
||||
clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
|
||||
clk_register_divider(dev, clk_name,
|
||||
clks[num++] = clk_register_divider(dev, clk_name,
|
||||
parent1, 0, pll_28nm->mmio +
|
||||
REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
|
||||
0, 8, 0, NULL);
|
||||
provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
|
||||
|
||||
snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
|
||||
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
|
||||
@ -581,22 +548,12 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
||||
|
||||
snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
|
||||
snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
|
||||
clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
|
||||
clk_register_fixed_factor(dev, clk_name,
|
||||
clks[num++] = clk_register_fixed_factor(dev, clk_name,
|
||||
parent1, CLK_SET_RATE_PARENT, 1, 4);
|
||||
provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
|
||||
|
||||
pll_28nm->num_clks = num;
|
||||
|
||||
pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
|
||||
pll_28nm->clk_data.clks = provided_clks;
|
||||
|
||||
ret = of_clk_add_provider(dev->of_node,
|
||||
of_clk_src_onecell_get, &pll_28nm->clk_data);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -625,14 +582,13 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
|
||||
}
|
||||
|
||||
pll = &pll_28nm->base;
|
||||
pll->cfg = phy->cfg;
|
||||
if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
|
||||
pll_28nm->vco_delay = 1000;
|
||||
else
|
||||
pll_28nm->vco_delay = 1;
|
||||
|
||||
pll->cfg = phy->cfg;
|
||||
|
||||
ret = pll_28nm_register(pll_28nm);
|
||||
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
|
||||
return ret;
|
||||
@ -802,7 +758,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
|
||||
.pll_init = dsi_pll_28nm_init,
|
||||
},
|
||||
.pll_ops = {
|
||||
.get_provider = dsi_pll_28nm_get_provider,
|
||||
.destroy = dsi_pll_28nm_destroy,
|
||||
.save_state = dsi_pll_28nm_save_state,
|
||||
.restore_state = dsi_pll_28nm_restore_state,
|
||||
@ -830,7 +785,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
|
||||
.pll_init = dsi_pll_28nm_init,
|
||||
},
|
||||
.pll_ops = {
|
||||
.get_provider = dsi_pll_28nm_get_provider,
|
||||
.destroy = dsi_pll_28nm_destroy,
|
||||
.save_state = dsi_pll_28nm_save_state,
|
||||
.restore_state = dsi_pll_28nm_restore_state,
|
||||
@ -858,7 +812,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
|
||||
.pll_init = dsi_pll_28nm_init,
|
||||
},
|
||||
.pll_ops = {
|
||||
.get_provider = dsi_pll_28nm_get_provider,
|
||||
.destroy = dsi_pll_28nm_destroy,
|
||||
.save_state = dsi_pll_28nm_save_state,
|
||||
.restore_state = dsi_pll_28nm_restore_state,
|
||||
|
||||
@ -39,15 +39,10 @@
|
||||
#define POLL_MAX_READS 8000
|
||||
#define POLL_TIMEOUT_US 1
|
||||
|
||||
#define NUM_PROVIDED_CLKS 2
|
||||
|
||||
#define VCO_REF_CLK_RATE 27000000
|
||||
#define VCO_MIN_RATE 600000000
|
||||
#define VCO_MAX_RATE 1200000000
|
||||
|
||||
#define DSI_BYTE_PLL_CLK 0
|
||||
#define DSI_PIXEL_PLL_CLK 1
|
||||
|
||||
#define VCO_PREF_DIV_RATIO 27
|
||||
|
||||
struct pll_28nm_cached_state {
|
||||
@ -76,10 +71,6 @@ struct dsi_pll_28nm {
|
||||
struct clk *clks[NUM_DSI_CLOCKS_MAX];
|
||||
u32 num_clks;
|
||||
|
||||
/* clock-provider: */
|
||||
struct clk *provided_clks[NUM_PROVIDED_CLKS];
|
||||
struct clk_onecell_data clk_data;
|
||||
|
||||
struct pll_28nm_cached_state cached_state;
|
||||
};
|
||||
|
||||
@ -377,30 +368,14 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
|
||||
struct clk **byte_clk_provider,
|
||||
struct clk **pixel_clk_provider)
|
||||
{
|
||||
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
||||
|
||||
if (byte_clk_provider)
|
||||
*byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
|
||||
if (pixel_clk_provider)
|
||||
*pixel_clk_provider =
|
||||
pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
|
||||
{
|
||||
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
||||
|
||||
msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
|
||||
pll_28nm->clks, pll_28nm->num_clks);
|
||||
msm_dsi_pll_helper_unregister_clks(pll_28nm->clks, pll_28nm->num_clks);
|
||||
}
|
||||
|
||||
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
||||
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)
|
||||
{
|
||||
char *clk_name, *parent_name, *vco_name;
|
||||
struct clk_init_data vco_init = {
|
||||
@ -411,10 +386,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
||||
};
|
||||
struct device *dev = &pll_28nm->pdev->dev;
|
||||
struct clk **clks = pll_28nm->clks;
|
||||
struct clk **provided_clks = pll_28nm->provided_clks;
|
||||
struct clk_bytediv *bytediv;
|
||||
struct clk_init_data bytediv_init = { };
|
||||
int ret, num = 0;
|
||||
int num = 0;
|
||||
|
||||
DBG("%d", pll_28nm->id);
|
||||
|
||||
@ -426,10 +400,6 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
||||
if (!vco_name)
|
||||
return -ENOMEM;
|
||||
|
||||
parent_name = devm_kzalloc(dev, 32, GFP_KERNEL);
|
||||
if (!parent_name)
|
||||
return -ENOMEM;
|
||||
|
||||
clk_name = devm_kzalloc(dev, 32, GFP_KERNEL);
|
||||
if (!clk_name)
|
||||
return -ENOMEM;
|
||||
@ -457,29 +427,19 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
||||
bytediv_init.num_parents = 1;
|
||||
|
||||
/* DIV2 */
|
||||
clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
|
||||
clk_register(dev, &bytediv->hw);
|
||||
clks[num++] = clk_register(dev, &bytediv->hw);
|
||||
provided_clocks[DSI_BYTE_PLL_CLK] = __clk_get_hw(clks[num - 1]);
|
||||
|
||||
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
|
||||
/* DIV3 */
|
||||
clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
|
||||
clk_register_divider(dev, clk_name,
|
||||
clks[num++] = clk_register_divider(dev, clk_name,
|
||||
parent_name, 0, pll_28nm->mmio +
|
||||
REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
|
||||
0, 8, 0, NULL);
|
||||
provided_clocks[DSI_PIXEL_PLL_CLK] = __clk_get_hw(clks[num - 1]);
|
||||
|
||||
pll_28nm->num_clks = num;
|
||||
|
||||
pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
|
||||
pll_28nm->clk_data.clks = provided_clks;
|
||||
|
||||
ret = of_clk_add_provider(dev->of_node,
|
||||
of_clk_src_onecell_get, &pll_28nm->clk_data);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -511,7 +471,7 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
|
||||
|
||||
pll->cfg = phy->cfg;
|
||||
|
||||
ret = pll_28nm_register(pll_28nm);
|
||||
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
|
||||
return ret;
|
||||
@ -702,7 +662,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
|
||||
.pll_init = dsi_pll_28nm_8960_init,
|
||||
},
|
||||
.pll_ops = {
|
||||
.get_provider = dsi_pll_28nm_get_provider,
|
||||
.destroy = dsi_pll_28nm_destroy,
|
||||
.save_state = dsi_pll_28nm_save_state,
|
||||
.restore_state = dsi_pll_28nm_restore_state,
|
||||
|
||||
@ -36,10 +36,6 @@
|
||||
* dsi0_pll_post_out_div_clk
|
||||
*/
|
||||
|
||||
#define DSI_BYTE_PLL_CLK 0
|
||||
#define DSI_PIXEL_PLL_CLK 1
|
||||
#define NUM_PROVIDED_CLKS 2
|
||||
|
||||
#define VCO_REF_CLK_RATE 19200000
|
||||
|
||||
struct dsi_pll_regs {
|
||||
@ -116,9 +112,6 @@ struct dsi_pll_7nm {
|
||||
struct clk_hw *pclk_mux_hw;
|
||||
struct clk_hw *out_dsiclk_hw;
|
||||
|
||||
/* clock-provider: */
|
||||
struct clk_hw_onecell_data *hw_data;
|
||||
|
||||
struct pll_7nm_cached_state cached_state;
|
||||
|
||||
enum msm_dsi_phy_usecase uc;
|
||||
@ -646,30 +639,11 @@ static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_pll_7nm_get_provider(struct msm_dsi_pll *pll,
|
||||
struct clk **byte_clk_provider,
|
||||
struct clk **pixel_clk_provider)
|
||||
{
|
||||
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
|
||||
struct clk_hw_onecell_data *hw_data = pll_7nm->hw_data;
|
||||
|
||||
DBG("DSI PLL%d", pll_7nm->id);
|
||||
|
||||
if (byte_clk_provider)
|
||||
*byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
|
||||
if (pixel_clk_provider)
|
||||
*pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll)
|
||||
{
|
||||
struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll);
|
||||
struct device *dev = &pll_7nm->pdev->dev;
|
||||
|
||||
DBG("DSI PLL%d", pll_7nm->id);
|
||||
of_clk_del_provider(dev->of_node);
|
||||
|
||||
clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
|
||||
clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
|
||||
@ -687,7 +661,7 @@ static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll)
|
||||
* state to follow the master PLL's divider/mux state. Therefore, we don't
|
||||
* require special clock ops that also configure the slave PLL registers
|
||||
*/
|
||||
static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
|
||||
static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks)
|
||||
{
|
||||
char clk_name[32], parent[32], vco_name[32];
|
||||
char parent2[32], parent3[32], parent4[32];
|
||||
@ -699,18 +673,11 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
|
||||
.ops = &clk_ops_dsi_pll_7nm_vco,
|
||||
};
|
||||
struct device *dev = &pll_7nm->pdev->dev;
|
||||
struct clk_hw_onecell_data *hw_data;
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
||||
DBG("DSI%d", pll_7nm->id);
|
||||
|
||||
hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
|
||||
NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
|
||||
GFP_KERNEL);
|
||||
if (!hw_data)
|
||||
return -ENOMEM;
|
||||
|
||||
snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->id);
|
||||
pll_7nm->base.clk_hw.init = &vco_init;
|
||||
|
||||
@ -762,7 +729,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
|
||||
}
|
||||
|
||||
pll_7nm->byte_clk_hw = hw;
|
||||
hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
|
||||
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
|
||||
|
||||
snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id);
|
||||
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->id);
|
||||
@ -822,22 +789,10 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
|
||||
}
|
||||
|
||||
pll_7nm->out_dsiclk_hw = hw;
|
||||
hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
|
||||
|
||||
hw_data->num = NUM_PROVIDED_CLKS;
|
||||
pll_7nm->hw_data = hw_data;
|
||||
|
||||
ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
|
||||
pll_7nm->hw_data);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
|
||||
goto err_dsiclk_hw;
|
||||
}
|
||||
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
|
||||
|
||||
return 0;
|
||||
|
||||
err_dsiclk_hw:
|
||||
clk_hw_unregister_divider(pll_7nm->out_dsiclk_hw);
|
||||
err_pclk_mux_hw:
|
||||
clk_hw_unregister_mux(pll_7nm->pclk_mux_hw);
|
||||
err_post_out_div_clk_hw:
|
||||
@ -893,7 +848,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
|
||||
|
||||
pll_7nm->vco_delay = 1;
|
||||
|
||||
ret = pll_7nm_register(pll_7nm);
|
||||
ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
|
||||
return ret;
|
||||
@ -1138,7 +1093,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
|
||||
.pll_init = dsi_pll_7nm_init,
|
||||
},
|
||||
.pll_ops = {
|
||||
.get_provider = dsi_pll_7nm_get_provider,
|
||||
.destroy = dsi_pll_7nm_destroy,
|
||||
.save_state = dsi_pll_7nm_save_state,
|
||||
.restore_state = dsi_pll_7nm_restore_state,
|
||||
@ -1165,7 +1119,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
|
||||
.pll_init = dsi_pll_7nm_init,
|
||||
},
|
||||
.pll_ops = {
|
||||
.get_provider = dsi_pll_7nm_get_provider,
|
||||
.destroy = dsi_pll_7nm_destroy,
|
||||
.save_state = dsi_pll_7nm_save_state,
|
||||
.restore_state = dsi_pll_7nm_restore_state,
|
||||
|
||||
@ -57,11 +57,8 @@ void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw)
|
||||
pll->pll_on = false;
|
||||
}
|
||||
|
||||
void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
|
||||
struct clk **clks, u32 num_clks)
|
||||
void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks)
|
||||
{
|
||||
of_clk_del_provider(pdev->dev.of_node);
|
||||
|
||||
if (!num_clks || !clks)
|
||||
return;
|
||||
|
||||
@ -74,17 +71,6 @@ void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
|
||||
/*
|
||||
* DSI PLL API
|
||||
*/
|
||||
int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
|
||||
struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
|
||||
{
|
||||
if (pll->cfg->pll_ops.get_provider)
|
||||
return pll->cfg->pll_ops.get_provider(pll,
|
||||
byte_clk_provider,
|
||||
pixel_clk_provider);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
|
||||
{
|
||||
if (pll->cfg->pll_ops.destroy)
|
||||
|
||||
@ -55,8 +55,7 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
|
||||
int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
|
||||
void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
|
||||
/* misc */
|
||||
void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
|
||||
struct clk **clks, u32 num_clks);
|
||||
void msm_dsi_pll_helper_unregister_clks(struct clk **clks, u32 num_clks);
|
||||
|
||||
#endif /* __DSI_PLL_H__ */
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user