dt-bindings: clock: samsung: convert Exynos7 to dtschema
Convert Samsung Exynos7 SoC clock controller bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220102115356.75796-4-krzysztof.kozlowski@canonical.com
This commit is contained in:
Krzysztof Kozlowski
Rob Herring
parent
23652cf52d
commit
5de80c3b57
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* Samsung Exynos7 Clock Controller
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Exynos7 clock controller has various blocks which are instantiated
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independently from the device-tree. These clock controllers
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generate and supply clocks to various hardware blocks within
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the SoC.
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Each clock is assigned an identifier and client nodes can use
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this identifier to specify the clock which they consume. All
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available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos7-clk.h header and can be used in
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device tree sources.
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External clocks:
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There are several clocks that are generated outside the SoC. It
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is expected that they are defined using standard clock bindings
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with following clock-output-names:
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- "fin_pll" - PLL input clock from XXTI
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Required Properties for Clock Controller:
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- compatible: clock controllers will use one of the following
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compatible strings to indicate the clock controller
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functionality.
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- "samsung,exynos7-clock-topc"
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- "samsung,exynos7-clock-top0"
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- "samsung,exynos7-clock-top1"
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- "samsung,exynos7-clock-ccore"
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- "samsung,exynos7-clock-peric0"
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- "samsung,exynos7-clock-peric1"
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- "samsung,exynos7-clock-peris"
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- "samsung,exynos7-clock-fsys0"
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- "samsung,exynos7-clock-fsys1"
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- "samsung,exynos7-clock-mscl"
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- "samsung,exynos7-clock-aud"
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- reg: physical base address of the controller and the length of
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memory mapped region.
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- #clock-cells: should be 1.
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- clocks: list of clock identifiers which are fed as the input to
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the given clock controller. Please refer the next section to
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find the input clocks for a given controller.
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- clock-names: list of names of clocks which are fed as the input
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to the given clock controller.
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Input clocks for top0 clock controller:
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- fin_pll
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- dout_sclk_bus0_pll
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- dout_sclk_bus1_pll
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- dout_sclk_cc_pll
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- dout_sclk_mfc_pll
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- dout_sclk_aud_pll
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Input clocks for top1 clock controller:
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- fin_pll
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- dout_sclk_bus0_pll
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- dout_sclk_bus1_pll
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- dout_sclk_cc_pll
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- dout_sclk_mfc_pll
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Input clocks for ccore clock controller:
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- fin_pll
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- dout_aclk_ccore_133
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Input clocks for peric0 clock controller:
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- fin_pll
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- dout_aclk_peric0_66
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- sclk_uart0
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Input clocks for peric1 clock controller:
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- fin_pll
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- dout_aclk_peric1_66
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- sclk_uart1
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- sclk_uart2
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- sclk_uart3
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- sclk_spi0
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- sclk_spi1
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- sclk_spi2
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- sclk_spi3
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- sclk_spi4
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- sclk_i2s1
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- sclk_pcm1
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- sclk_spdif
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Input clocks for peris clock controller:
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- fin_pll
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- dout_aclk_peris_66
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Input clocks for fsys0 clock controller:
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- fin_pll
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- dout_aclk_fsys0_200
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- dout_sclk_mmc2
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Input clocks for fsys1 clock controller:
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- fin_pll
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- dout_aclk_fsys1_200
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- dout_sclk_mmc0
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- dout_sclk_mmc1
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Input clocks for aud clock controller:
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- fin_pll
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- fout_aud_pll
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@ -0,0 +1,269 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos7 SoC clock controller
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maintainers:
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Tomasz Figa <tomasz.figa@gmail.com>
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description: |
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Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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name::
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- "fin_pll" - PLL input clock from XXTI
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All available clocks are defined as preprocessor macros in
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include/dt-bindings/clock/exynos7-clk.h header.
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properties:
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compatible:
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enum:
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- samsung,exynos7-clock-topc
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- samsung,exynos7-clock-top0
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- samsung,exynos7-clock-top1
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- samsung,exynos7-clock-ccore
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- samsung,exynos7-clock-peric0
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- samsung,exynos7-clock-peric1
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- samsung,exynos7-clock-peris
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- samsung,exynos7-clock-fsys0
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- samsung,exynos7-clock-fsys1
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- samsung,exynos7-clock-mscl
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- samsung,exynos7-clock-aud
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clocks:
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minItems: 1
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maxItems: 13
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clock-names:
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minItems: 1
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maxItems: 13
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- "#clock-cells"
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-top0
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then:
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properties:
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: fin_pll
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- const: dout_sclk_bus0_pll
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- const: dout_sclk_bus1_pll
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- const: dout_sclk_cc_pll
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- const: dout_sclk_mfc_pll
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- const: dout_sclk_aud_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-top1
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: fin_pll
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- const: dout_sclk_bus0_pll
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- const: dout_sclk_bus1_pll
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- const: dout_sclk_cc_pll
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- const: dout_sclk_mfc_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-ccore
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_ccore_133
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-peric0
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_peric0_66
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- const: sclk_uart0
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-peric1
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then:
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properties:
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clocks:
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minItems: 13
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maxItems: 13
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_peric1_66
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- const: sclk_uart1
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- const: sclk_uart2
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- const: sclk_uart3
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- const: sclk_spi0
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- const: sclk_spi1
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- const: sclk_spi2
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- const: sclk_spi3
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- const: sclk_spi4
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- const: sclk_i2s1
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- const: sclk_pcm1
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- const: sclk_spdif
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-peris
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_peris_66
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-fsys0
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_fsys0_200
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- const: dout_sclk_mmc2
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-fsys1
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_fsys1_200
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- const: dout_sclk_mmc0
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- const: dout_sclk_mmc1
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-aud
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: fout_aud_pll
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required:
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- clock-names
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos7-clk.h>
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fin_pll: clock {
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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clock-controller@105e0000 {
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compatible = "samsung,exynos7-clock-top1";
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reg = <0x105e0000 0xb000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_topc DOUT_SCLK_BUS0_PLL>,
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<&clock_topc DOUT_SCLK_BUS1_PLL>,
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<&clock_topc DOUT_SCLK_CC_PLL>,
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<&clock_topc DOUT_SCLK_MFC_PLL>;
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clock-names = "fin_pll",
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"dout_sclk_bus0_pll",
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"dout_sclk_bus1_pll",
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"dout_sclk_cc_pll",
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"dout_sclk_mfc_pll";
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};
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