dt-bindings: net: dsa: qca8k: support internal mdio-bus

This patch updates the qca8k's binding to document to the
approach for using the internal mdio-bus of the supported
qca8k switches.

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Christian Lamparter 2019-03-22 01:05:01 +01:00 committed by David S. Miller
parent fb1eb41a3d
commit 5e07321f33

View File

@ -12,10 +12,15 @@ Required properties:
Subnodes: Subnodes:
The integrated switch subnode should be specified according to the binding The integrated switch subnode should be specified according to the binding
described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
port and PHY id, each subnode describing a port needs to have a valid phandle mdio-bus each subnode describing a port needs to have a valid phandle
referencing the internal PHY connected to it. The CPU port of this switch is referencing the internal PHY it is connected to. This is because there's no
always port 0. N:N mapping of port and PHY id.
Don't use mixed external and internal mdio-bus configurations, as this is
not supported by the hardware.
The CPU port of this switch is always port 0.
A CPU port node has the following optional node: A CPU port node has the following optional node:
@ -31,8 +36,9 @@ For QCA8K the 'fixed-link' sub-node supports only the following properties:
- 'full-duplex' (boolean, optional), to indicate that full duplex is - 'full-duplex' (boolean, optional), to indicate that full duplex is
used. When absent, half duplex is assumed. used. When absent, half duplex is assumed.
Example: Examples:
for the external mdio-bus configuration:
&mdio0 { &mdio0 {
phy_port1: phy@0 { phy_port1: phy@0 {
@ -108,3 +114,56 @@ Example:
}; };
}; };
}; };
for the internal master mdio-bus configuration:
&mdio0 {
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
speed = 1000;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port@5 {
reg = <5>;
label = "wan";
};
};
};
};