iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/hisilicon/hibmc: Add hisilicon hibmc drm master driver

Browse Source 
Add DRM master driver for Hisilicon Hibmc SoC which used for
Out-of-band management. Blow is the general hardware connection,
both the Hibmc and the host CPU are on the same mother board.

+----------+       +----------+
|          | PCIe  |  Hibmc   |
|host CPU( |<----->| display  |
|arm64,x86)|       |subsystem |
+----------+       +----------+

Signed-off-by: Rongrong Zou <zourongrong@gmail.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Xinliang Liu <xinliang.liu@linaro.org>
Acked-by: Sean Paul <seanpaul@chromium.org>
This commit is contained in:
Rongrong Zou 2016-11-16 17:15:34 +08:00
parent b7c0e47d98
commit 5e0df3a08f
7 changed files with 560 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/hisilicon/Kconfig
View File

@ -2,4 +2,5 @@
# hisilicon drm device configuration.
# Please keep this list sorted alphabetically
source "drivers/gpu/drm/hisilicon/hibmc/Kconfig"
source "drivers/gpu/drm/hisilicon/kirin/Kconfig"

1
drivers/gpu/drm/hisilicon/Makefile
View File

@ -2,4 +2,5 @@
# Makefile for hisilicon drm drivers.
# Please keep this list sorted alphabetically
obj-$(CONFIG_DRM_HISI_HIBMC) += hibmc/
obj-$(CONFIG_DRM_HISI_KIRIN) += kirin/

9
drivers/gpu/drm/hisilicon/hibmc/Kconfig Normal file
View File

@ -0,0 +1,9 @@
config DRM_HISI_HIBMC
tristate "DRM Support for Hisilicon Hibmc"
depends on DRM && PCI
select DRM_KMS_HELPER
select DRM_TTM
help
Choose this option if you have a Hisilicon Hibmc soc chipset.
If M is selected the module will be called hibmc-drm.

4
drivers/gpu/drm/hisilicon/hibmc/Makefile Normal file
View File

@ -0,0 +1,4 @@
ccflags-y := -Iinclude/drm
hibmc-drm-y := hibmc_drm_drv.o
obj-$(CONFIG_DRM_HISI_HIBMC) += hibmc-drm.o

308
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c Normal file
View File

@ -0,0 +1,308 @@
/* Hisilicon Hibmc SoC drm driver
*
* Based on the bochs drm driver.
*
* Copyright (c) 2016 Huawei Limited.
*
* Author:
* Rongrong Zou <zourongrong@huawei.com>
* Rongrong Zou <zourongrong@gmail.com>
* Jianhua Li <lijianhua@huawei.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/console.h>
#include <linux/module.h>
#include "hibmc_drm_drv.h"
#include "hibmc_drm_regs.h"
static const struct file_operations hibmc_fops = {
.owner = THIS_MODULE,
.open = drm_open,
.release = drm_release,
.unlocked_ioctl = drm_ioctl,
.compat_ioctl = drm_compat_ioctl,
.poll = drm_poll,
.read = drm_read,
.llseek = no_llseek,
};
static int hibmc_enable_vblank(struct drm_device *dev, unsigned int pipe)
{
return 0;
}
static void hibmc_disable_vblank(struct drm_device *dev, unsigned int pipe)
{
}
static struct drm_driver hibmc_driver = {
.fops = &hibmc_fops,
.name = "hibmc",
.date = "20160828",
.desc = "hibmc drm driver",
.major = 1,
.minor = 0,
.get_vblank_counter = drm_vblank_no_hw_counter,
.enable_vblank = hibmc_enable_vblank,
.disable_vblank = hibmc_disable_vblank,
};
static int hibmc_pm_suspend(struct device *dev)
{
return 0;
}
static int hibmc_pm_resume(struct device *dev)
{
return 0;
}
static const struct dev_pm_ops hibmc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend,
hibmc_pm_resume)
};
/*
* It can operate in one of three modes: 0, 1 or Sleep.
*/
void hibmc_set_power_mode(struct hibmc_drm_private *priv,
unsigned int power_mode)
{
unsigned int control_value = 0;
void __iomem *mmio = priv->mmio;
unsigned int input = 1;
if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP)
return;
if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP)
input = 0;
control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
HIBMC_PW_MODE_CTL_OSC_INPUT_MASK);
control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
}
void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate)
{
unsigned int gate_reg;
unsigned int mode;
void __iomem *mmio = priv->mmio;
/* Get current power mode. */
mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) &
HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT;
switch (mode) {
case HIBMC_PW_MODE_CTL_MODE_MODE0:
gate_reg = HIBMC_MODE0_GATE;
break;
case HIBMC_PW_MODE_CTL_MODE_MODE1:
gate_reg = HIBMC_MODE1_GATE;
break;
default:
gate_reg = HIBMC_MODE0_GATE;
break;
}
writel(gate, mmio + gate_reg);
}
static void hibmc_hw_config(struct hibmc_drm_private *priv)
{
unsigned int reg;
/* On hardware reset, power mode 0 is default. */
hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
/* Enable display power gate & LOCALMEM power gate*/
reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
reg |= HIBMC_CURR_GATE_DISPLAY(1);
reg |= HIBMC_CURR_GATE_LOCALMEM(1);
hibmc_set_current_gate(priv, reg);
/*
* Reset the memory controller. If the memory controller
* is not reset in chip,the system might hang when sw accesses
* the memory.The memory should be resetted after
* changing the MXCLK.
*/
reg = readl(priv->mmio + HIBMC_MISC_CTRL);
reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0);
writel(reg, priv->mmio + HIBMC_MISC_CTRL);
reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1);
writel(reg, priv->mmio + HIBMC_MISC_CTRL);
}
static int hibmc_hw_map(struct hibmc_drm_private *priv)
{
struct drm_device *dev = priv->dev;
struct pci_dev *pdev = dev->pdev;
resource_size_t addr, size, ioaddr, iosize;
ioaddr = pci_resource_start(pdev, 1);
iosize = pci_resource_len(pdev, 1);
priv->mmio = devm_ioremap_nocache(dev->dev, ioaddr, iosize);
if (!priv->mmio) {
DRM_ERROR("Cannot map mmio region\n");
return -ENOMEM;
}
addr = pci_resource_start(pdev, 0);
size = pci_resource_len(pdev, 0);
priv->fb_map = devm_ioremap(dev->dev, addr, size);
if (!priv->fb_map) {
DRM_ERROR("Cannot map framebuffer\n");
return -ENOMEM;
}
priv->fb_base = addr;
priv->fb_size = size;
return 0;
}
static int hibmc_hw_init(struct hibmc_drm_private *priv)
{
int ret;
ret = hibmc_hw_map(priv);
if (ret)
return ret;
hibmc_hw_config(priv);
return 0;
}
static int hibmc_unload(struct drm_device *dev)
{
return 0;
}
static int hibmc_load(struct drm_device *dev)
{
struct hibmc_drm_private *priv;
int ret;
priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv) {
DRM_ERROR("no memory to allocate for hibmc_drm_private\n");
return -ENOMEM;
}
dev->dev_private = priv;
priv->dev = dev;
ret = hibmc_hw_init(priv);
if (ret)
goto err;
return 0;
err:
hibmc_unload(dev);
DRM_ERROR("failed to initialize drm driver: %d\n", ret);
return ret;
}
static int hibmc_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct drm_device *dev;
int ret;
dev = drm_dev_alloc(&hibmc_driver, &pdev->dev);
if (!dev) {
DRM_ERROR("failed to allocate drm_device\n");
return -ENOMEM;
}
dev->pdev = pdev;
pci_set_drvdata(pdev, dev);
ret = pci_enable_device(pdev);
if (ret) {
DRM_ERROR("failed to enable pci device: %d\n", ret);
goto err_free;
}
ret = hibmc_load(dev);
if (ret) {
DRM_ERROR("failed to load hibmc: %d\n", ret);
goto err_disable;
}
ret = drm_dev_register(dev, 0);
if (ret) {
DRM_ERROR("failed to register drv for userspace access: %d\n",
ret);
goto err_unload;
}
return 0;
err_unload:
hibmc_unload(dev);
err_disable:
pci_disable_device(pdev);
err_free:
drm_dev_unref(dev);
return ret;
}
static void hibmc_pci_remove(struct pci_dev *pdev)
{
struct drm_device *dev = pci_get_drvdata(pdev);
drm_dev_unregister(dev);
hibmc_unload(dev);
drm_dev_unref(dev);
}
static struct pci_device_id hibmc_pci_table[] = {
{0x19e5, 0x1711, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0,}
};
static struct pci_driver hibmc_pci_driver = {
.name = "hibmc-drm",
.id_table = hibmc_pci_table,
.probe = hibmc_pci_probe,
.remove = hibmc_pci_remove,
.driver.pm = &hibmc_pm_ops,
};
static int __init hibmc_init(void)
{
return pci_register_driver(&hibmc_pci_driver);
}
static void __exit hibmc_exit(void)
{
return pci_unregister_driver(&hibmc_pci_driver);
}
module_init(hibmc_init);
module_exit(hibmc_exit);
MODULE_DEVICE_TABLE(pci, hibmc_pci_table);
MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>");
MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc");
MODULE_LICENSE("GPL v2");

41
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h Normal file
View File

@ -0,0 +1,41 @@
/* Hisilicon Hibmc SoC drm driver
*
* Based on the bochs drm driver.
*
* Copyright (c) 2016 Huawei Limited.
*
* Author:
* Rongrong Zou <zourongrong@huawei.com>
* Rongrong Zou <zourongrong@gmail.com>
* Jianhua Li <lijianhua@huawei.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef HIBMC_DRM_DRV_H
#define HIBMC_DRM_DRV_H
#include <drm/drmP.h>
struct hibmc_drm_private {
/* hw */
void __iomem *mmio;
void __iomem *fb_map;
unsigned long fb_base;
unsigned long fb_size;
/* drm */
struct drm_device *dev;
};
void hibmc_set_power_mode(struct hibmc_drm_private *priv,
unsigned int power_mode);
void hibmc_set_current_gate(struct hibmc_drm_private *priv,
unsigned int gate);
#endif

196
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h Normal file
View File

@ -0,0 +1,196 @@
/* Hisilicon Hibmc SoC drm driver
*
* Based on the bochs drm driver.
*
* Copyright (c) 2016 Huawei Limited.
*
* Author:
* Rongrong Zou <zourongrong@huawei.com>
* Rongrong Zou <zourongrong@gmail.com>
* Jianhua Li <lijianhua@huawei.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef HIBMC_DRM_HW_H
#define HIBMC_DRM_HW_H
/* register definition */
#define HIBMC_MISC_CTRL 0x4
#define HIBMC_MSCCTL_LOCALMEM_RESET(x) ((x) << 6)
#define HIBMC_MSCCTL_LOCALMEM_RESET_MASK 0x40
#define HIBMC_CURRENT_GATE 0x000040
#define HIBMC_CURR_GATE_DISPLAY(x) ((x) << 2)
#define HIBMC_CURR_GATE_DISPLAY_MASK 0x4
#define HIBMC_CURR_GATE_LOCALMEM(x) ((x) << 1)
#define HIBMC_CURR_GATE_LOCALMEM_MASK 0x2
#define HIBMC_MODE0_GATE 0x000044
#define HIBMC_MODE1_GATE 0x000048
#define HIBMC_POWER_MODE_CTRL 0x00004C
#define HIBMC_PW_MODE_CTL_OSC_INPUT(x) ((x) << 3)
#define HIBMC_PW_MODE_CTL_OSC_INPUT_MASK 0x8
#define HIBMC_PW_MODE_CTL_MODE(x) ((x) << 0)
#define HIBMC_PW_MODE_CTL_MODE_MASK 0x03
#define HIBMC_PW_MODE_CTL_MODE_SHIFT 0
#define HIBMC_PW_MODE_CTL_MODE_MODE0 0
#define HIBMC_PW_MODE_CTL_MODE_MODE1 1
#define HIBMC_PW_MODE_CTL_MODE_SLEEP 2
#define HIBMC_PANEL_PLL_CTRL 0x00005C
#define HIBMC_CRT_PLL_CTRL 0x000060
#define HIBMC_PLL_CTRL_BYPASS(x) ((x) << 18)
#define HIBMC_PLL_CTRL_BYPASS_MASK 0x40000
#define HIBMC_PLL_CTRL_POWER(x) ((x) << 17)
#define HIBMC_PLL_CTRL_POWER_MASK 0x20000
#define HIBMC_PLL_CTRL_INPUT(x) ((x) << 16)
#define HIBMC_PLL_CTRL_INPUT_MASK 0x10000
#define HIBMC_PLL_CTRL_POD(x) ((x) << 14)
#define HIBMC_PLL_CTRL_POD_MASK 0xC000
#define HIBMC_PLL_CTRL_OD(x) ((x) << 12)
#define HIBMC_PLL_CTRL_OD_MASK 0x3000
#define HIBMC_PLL_CTRL_N(x) ((x) << 8)
#define HIBMC_PLL_CTRL_N_MASK 0xF00
#define HIBMC_PLL_CTRL_M(x) ((x) << 0)
#define HIBMC_PLL_CTRL_M_MASK 0xFF
#define HIBMC_CRT_DISP_CTL 0x80200
#define HIBMC_CRT_DISP_CTL_CRTSELECT(x) ((x) << 25)
#define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK 0x2000000
#define HIBMC_CRTSELECT_CRT 1
#define HIBMC_CRT_DISP_CTL_CLOCK_PHASE(x) ((x) << 14)
#define HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK 0x4000
#define HIBMC_CRT_DISP_CTL_VSYNC_PHASE(x) ((x) << 13)
#define HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK 0x2000
#define HIBMC_CRT_DISP_CTL_HSYNC_PHASE(x) ((x) << 12)
#define HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK 0x1000
#define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8)
#define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x100
#define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2)
#define HIBMC_CRT_DISP_CTL_PLANE_MASK 4
#define HIBMC_CRT_DISP_CTL_FORMAT(x) ((x) << 0)
#define HIBMC_CRT_DISP_CTL_FORMAT_MASK 0x03
#define HIBMC_CRT_FB_ADDRESS 0x080204
#define HIBMC_CRT_FB_WIDTH 0x080208
#define HIBMC_CRT_FB_WIDTH_WIDTH(x) ((x) << 16)
#define HIBMC_CRT_FB_WIDTH_WIDTH_MASK 0x3FFF0000
#define HIBMC_CRT_FB_WIDTH_OFFS(x) ((x) << 0)
#define HIBMC_CRT_FB_WIDTH_OFFS_MASK 0x3FFF
#define HIBMC_CRT_HORZ_TOTAL 0x08020C
#define HIBMC_CRT_HORZ_TOTAL_TOTAL(x) ((x) << 16)
#define HIBMC_CRT_HORZ_TOTAL_TOTAL_MASK 0xFFF0000
#define HIBMC_CRT_HORZ_TOTAL_DISP_END(x) ((x) << 0)
#define HIBMC_CRT_HORZ_TOTAL_DISP_END_MASK 0xFFF
#define HIBMC_CRT_HORZ_SYNC 0x080210
#define HIBMC_CRT_HORZ_SYNC_WIDTH(x) ((x) << 16)
#define HIBMC_CRT_HORZ_SYNC_WIDTH_MASK 0xFF0000
#define HIBMC_CRT_HORZ_SYNC_START(x) ((x) << 0)
#define HIBMC_CRT_HORZ_SYNC_START_MASK 0xFFF
#define HIBMC_CRT_VERT_TOTAL 0x080214
#define HIBMC_CRT_VERT_TOTAL_TOTAL(x) ((x) << 16)
#define HIBMC_CRT_VERT_TOTAL_TOTAL_MASK 0x7FFF0000
#define HIBMC_CRT_VERT_TOTAL_DISP_END(x) ((x) << 0)
#define HIBMC_CRT_VERT_TOTAL_DISP_END_MASK 0x7FF
#define HIBMC_CRT_VERT_SYNC 0x080218
#define HIBMC_CRT_VERT_SYNC_HEIGHT(x) ((x) << 16)
#define HIBMC_CRT_VERT_SYNC_HEIGHT_MASK 0x3F0000
#define HIBMC_CRT_VERT_SYNC_START(x) ((x) << 0)
#define HIBMC_CRT_VERT_SYNC_START_MASK 0x7FF
/* Auto Centering */
#define HIBMC_CRT_AUTO_CENTERING_TL 0x080280
#define HIBMC_CRT_AUTO_CENTERING_TL_TOP(x) ((x) << 16)
#define HIBMC_CRT_AUTO_CENTERING_TL_TOP_MASK 0x7FF0000
#define HIBMC_CRT_AUTO_CENTERING_TL_LEFT(x) ((x) << 0)
#define HIBMC_CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7FF
#define HIBMC_CRT_AUTO_CENTERING_BR 0x080284
#define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM(x) ((x) << 16)
#define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM_MASK 0x7FF0000
#define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT(x) ((x) << 0)
#define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7FF
/* register to control panel output */
#define HIBMC_DISPLAY_CONTROL_HISILE 0x80288
#define HIBMC_DISPLAY_CONTROL_FPVDDEN(x) ((x) << 0)
#define HIBMC_DISPLAY_CONTROL_PANELDATE(x) ((x) << 1)
#define HIBMC_DISPLAY_CONTROL_FPEN(x) ((x) << 2)
#define HIBMC_DISPLAY_CONTROL_VBIASEN(x) ((x) << 3)
#define HIBMC_RAW_INTERRUPT 0x80290
#define HIBMC_RAW_INTERRUPT_VBLANK(x) ((x) << 2)
#define HIBMC_RAW_INTERRUPT_VBLANK_MASK 0x4
#define HIBMC_RAW_INTERRUPT_EN 0x80298
#define HIBMC_RAW_INTERRUPT_EN_VBLANK(x) ((x) << 2)
#define HIBMC_RAW_INTERRUPT_EN_VBLANK_MASK 0x4
/* register and values for PLL control */
#define CRT_PLL1_HS 0x802a8
#define CRT_PLL1_HS_OUTER_BYPASS(x) ((x) << 30)
#define CRT_PLL1_HS_INTER_BYPASS(x) ((x) << 29)
#define CRT_PLL1_HS_POWERON(x) ((x) << 24)
#define CRT_PLL1_HS_25MHZ 0x23d40f02
#define CRT_PLL1_HS_40MHZ 0x23940801
#define CRT_PLL1_HS_65MHZ 0x23940d01
#define CRT_PLL1_HS_78MHZ 0x23540F82
#define CRT_PLL1_HS_74MHZ 0x23941dc2
#define CRT_PLL1_HS_80MHZ 0x23941001
#define CRT_PLL1_HS_80MHZ_1152 0x23540fc2
#define CRT_PLL1_HS_108MHZ 0x23b41b01
#define CRT_PLL1_HS_162MHZ 0x23480681
#define CRT_PLL1_HS_148MHZ 0x23541dc2
#define CRT_PLL1_HS_193MHZ 0x234807c1
#define CRT_PLL2_HS 0x802ac
#define CRT_PLL2_HS_25MHZ 0x206B851E
#define CRT_PLL2_HS_40MHZ 0x30000000
#define CRT_PLL2_HS_65MHZ 0x40000000
#define CRT_PLL2_HS_78MHZ 0x50E147AE
#define CRT_PLL2_HS_74MHZ 0x602B6AE7
#define CRT_PLL2_HS_80MHZ 0x70000000
#define CRT_PLL2_HS_108MHZ 0x80000000
#define CRT_PLL2_HS_162MHZ 0xA0000000
#define CRT_PLL2_HS_148MHZ 0xB0CCCCCD
#define CRT_PLL2_HS_193MHZ 0xC0872B02
#define HIBMC_FIELD(field, value) (field(value) & field##_MASK)
#endif