firmware: xilinx: Remove eemi ops for clock_getstate
Use direct function call instead of eemi ops for clock_getstate. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-7-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -77,9 +77,8 @@ static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int state, ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_getstate(clk_id, &state);
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ret = zynqmp_pm_clock_getstate(clk_id, &state);
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if (ret) {
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pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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@ -222,9 +222,8 @@ static int zynqmp_pll_is_enabled(struct clk_hw *hw)
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u32 clk_id = clk->clk_id;
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unsigned int state;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_getstate(clk_id, &state);
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ret = zynqmp_pm_clock_getstate(clk_id, &state);
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if (ret) {
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pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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@ -382,7 +382,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_disable);
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*
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* Return: Returns status, either success or error+reason
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*/
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static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
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int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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@ -393,6 +393,7 @@ static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getstate);
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/**
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* zynqmp_pm_clock_setdivider() - Set the clock divider for given id
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@ -739,7 +740,6 @@ static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
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}
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static const struct zynqmp_eemi_ops eemi_ops = {
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.clock_getstate = zynqmp_pm_clock_getstate,
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.clock_setdivider = zynqmp_pm_clock_setdivider,
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.clock_getdivider = zynqmp_pm_clock_getdivider,
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.clock_setrate = zynqmp_pm_clock_setrate,
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@ -296,7 +296,6 @@ struct zynqmp_pm_query_data {
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struct zynqmp_eemi_ops {
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int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
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int (*fpga_get_status)(u32 *value);
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int (*clock_getstate)(u32 clock_id, u32 *state);
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int (*clock_setdivider)(u32 clock_id, u32 divider);
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int (*clock_getdivider)(u32 clock_id, u32 *divider);
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int (*clock_setrate)(u32 clock_id, u64 rate);
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@ -331,6 +330,7 @@ int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
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int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
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int zynqmp_pm_clock_enable(u32 clock_id);
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int zynqmp_pm_clock_disable(u32 clock_id);
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int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
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#else
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static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
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{
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@ -357,6 +357,10 @@ static inline int zynqmp_pm_clock_disable(u32 clock_id)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
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{
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return -ENODEV;
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}
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#endif
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#endif /* __FIRMWARE_ZYNQMP_H__ */
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