drm/amd/display: Move DCC support functions into dchubbub
Added dchububu.h header file for common enum/struct definitions. Added new interface functions get_dcc_compression_cap, dcc_support_swizzle, dcc_support_pixel_format. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Bernstein
Alex Deucher
parent
c4b0faae71
commit
5ebfb7a599
@ -476,8 +476,227 @@ void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
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DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
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}
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static bool hubbub1_dcc_support_swizzle(
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enum swizzle_mode_values swizzle,
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unsigned int bytes_per_element,
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enum segment_order *segment_order_horz,
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enum segment_order *segment_order_vert)
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{
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bool standard_swizzle = false;
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bool display_swizzle = false;
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switch (swizzle) {
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case DC_SW_4KB_S:
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case DC_SW_64KB_S:
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case DC_SW_VAR_S:
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case DC_SW_4KB_S_X:
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case DC_SW_64KB_S_X:
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case DC_SW_VAR_S_X:
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standard_swizzle = true;
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break;
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case DC_SW_4KB_D:
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case DC_SW_64KB_D:
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case DC_SW_VAR_D:
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case DC_SW_4KB_D_X:
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case DC_SW_64KB_D_X:
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case DC_SW_VAR_D_X:
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display_swizzle = true;
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break;
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default:
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break;
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}
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if (bytes_per_element == 1 && standard_swizzle) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__na;
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return true;
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}
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if (bytes_per_element == 2 && standard_swizzle) {
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*segment_order_horz = segment_order__non_contiguous;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 4 && standard_swizzle) {
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*segment_order_horz = segment_order__non_contiguous;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 8 && standard_swizzle) {
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*segment_order_horz = segment_order__na;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 8 && display_swizzle) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__non_contiguous;
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return true;
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}
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return false;
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}
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static bool hubbub1_dcc_support_pixel_format(
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enum surface_pixel_format format,
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unsigned int *bytes_per_element)
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{
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/* DML: get_bytes_per_element */
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switch (format) {
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
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case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
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*bytes_per_element = 2;
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return true;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
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*bytes_per_element = 4;
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return true;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
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*bytes_per_element = 8;
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return true;
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default:
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return false;
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}
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}
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static void hubbub1_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
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unsigned int bytes_per_element)
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{
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/* copied from DML. might want to refactor DML to leverage from DML */
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/* DML : get_blk256_size */
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if (bytes_per_element == 1) {
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*blk256_width = 16;
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*blk256_height = 16;
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} else if (bytes_per_element == 2) {
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*blk256_width = 16;
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*blk256_height = 8;
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} else if (bytes_per_element == 4) {
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*blk256_width = 8;
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*blk256_height = 8;
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} else if (bytes_per_element == 8) {
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*blk256_width = 8;
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*blk256_height = 4;
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}
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}
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static void hubbub1_det_request_size(
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unsigned int height,
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unsigned int width,
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unsigned int bpe,
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bool *req128_horz_wc,
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bool *req128_vert_wc)
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{
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unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
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unsigned int blk256_height = 0;
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unsigned int blk256_width = 0;
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unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
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hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
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swath_bytes_horz_wc = height * blk256_height * bpe;
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swath_bytes_vert_wc = width * blk256_width * bpe;
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*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
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false : /* full 256B request */
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true; /* half 128b request */
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*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
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false : /* full 256B request */
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true; /* half 128b request */
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}
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static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub,
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const struct dc_dcc_surface_param *input,
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struct dc_surface_dcc_cap *output)
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{
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struct dc *dc = hubbub->ctx->dc;
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/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
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enum dcc_control dcc_control;
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unsigned int bpe;
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enum segment_order segment_order_horz, segment_order_vert;
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bool req128_horz_wc, req128_vert_wc;
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memset(output, 0, sizeof(*output));
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if (dc->debug.disable_dcc == DCC_DISABLE)
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return false;
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if (!hubbub->funcs->dcc_support_pixel_format(input->format, &bpe))
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return false;
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if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
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&segment_order_horz, &segment_order_vert))
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return false;
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hubbub1_det_request_size(input->surface_size.height, input->surface_size.width,
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bpe, &req128_horz_wc, &req128_vert_wc);
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if (!req128_horz_wc && !req128_vert_wc) {
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dcc_control = dcc_control__256_256_xxx;
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} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
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if (!req128_horz_wc)
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dcc_control = dcc_control__256_256_xxx;
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else if (segment_order_horz == segment_order__contiguous)
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dcc_control = dcc_control__128_128_xxx;
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else
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dcc_control = dcc_control__256_64_64;
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} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
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if (!req128_vert_wc)
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dcc_control = dcc_control__256_256_xxx;
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else if (segment_order_vert == segment_order__contiguous)
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dcc_control = dcc_control__128_128_xxx;
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else
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dcc_control = dcc_control__256_64_64;
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} else {
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if ((req128_horz_wc &&
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segment_order_horz == segment_order__non_contiguous) ||
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(req128_vert_wc &&
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segment_order_vert == segment_order__non_contiguous))
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/* access_dir not known, must use most constraining */
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dcc_control = dcc_control__256_64_64;
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else
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/* reg128 is true for either horz and vert
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* but segment_order is contiguous
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*/
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dcc_control = dcc_control__128_128_xxx;
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}
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if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
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dcc_control != dcc_control__256_256_xxx)
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return false;
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switch (dcc_control) {
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case dcc_control__256_256_xxx:
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output->grph.rgb.max_uncompressed_blk_size = 256;
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output->grph.rgb.max_compressed_blk_size = 256;
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output->grph.rgb.independent_64b_blks = false;
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break;
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case dcc_control__128_128_xxx:
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output->grph.rgb.max_uncompressed_blk_size = 128;
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output->grph.rgb.max_compressed_blk_size = 128;
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output->grph.rgb.independent_64b_blks = false;
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break;
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case dcc_control__256_64_64:
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output->grph.rgb.max_uncompressed_blk_size = 256;
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output->grph.rgb.max_compressed_blk_size = 64;
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output->grph.rgb.independent_64b_blks = true;
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break;
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}
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output->capable = true;
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output->const_color_support = false;
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return true;
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}
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static const struct hubbub_funcs hubbub1_funcs = {
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.update_dchub = hubbub1_update_dchub
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.update_dchub = hubbub1_update_dchub,
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.dcc_support_swizzle = hubbub1_dcc_support_swizzle,
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.dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,
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.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
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};
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void hubbub1_construct(struct hubbub *hubbub,
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@ -27,6 +27,7 @@
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#define __DC_HUBBUB_DCN10_H__
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#include "core_types.h"
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#include "dchubbub.h"
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#define HUBHUB_REG_LIST_DCN()\
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SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
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@ -173,12 +174,6 @@ struct dcn_hubbub_wm {
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struct dcn_hubbub_wm_set sets[4];
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};
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struct hubbub_funcs {
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void (*update_dchub)(
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struct hubbub *hubbub,
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struct dchub_init_data *dh_data);
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};
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struct hubbub {
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const struct hubbub_funcs *funcs;
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struct dc_context *ctx;
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@ -937,235 +937,16 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
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return idle_pipe;
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}
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enum dcc_control {
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dcc_control__256_256_xxx,
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dcc_control__128_128_xxx,
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dcc_control__256_64_64,
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};
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enum segment_order {
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segment_order__na,
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segment_order__contiguous,
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segment_order__non_contiguous,
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};
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static bool dcc_support_pixel_format(
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enum surface_pixel_format format,
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unsigned int *bytes_per_element)
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{
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/* DML: get_bytes_per_element */
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switch (format) {
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
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case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
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*bytes_per_element = 2;
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return true;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
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*bytes_per_element = 4;
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return true;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
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*bytes_per_element = 8;
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return true;
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default:
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return false;
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}
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}
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static bool dcc_support_swizzle(
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enum swizzle_mode_values swizzle,
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unsigned int bytes_per_element,
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enum segment_order *segment_order_horz,
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enum segment_order *segment_order_vert)
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{
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bool standard_swizzle = false;
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bool display_swizzle = false;
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switch (swizzle) {
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case DC_SW_4KB_S:
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case DC_SW_64KB_S:
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case DC_SW_VAR_S:
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case DC_SW_4KB_S_X:
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case DC_SW_64KB_S_X:
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case DC_SW_VAR_S_X:
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standard_swizzle = true;
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break;
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case DC_SW_4KB_D:
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case DC_SW_64KB_D:
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case DC_SW_VAR_D:
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case DC_SW_4KB_D_X:
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case DC_SW_64KB_D_X:
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case DC_SW_VAR_D_X:
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display_swizzle = true;
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break;
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default:
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break;
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}
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if (bytes_per_element == 1 && standard_swizzle) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__na;
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return true;
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}
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if (bytes_per_element == 2 && standard_swizzle) {
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*segment_order_horz = segment_order__non_contiguous;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 4 && standard_swizzle) {
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*segment_order_horz = segment_order__non_contiguous;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 8 && standard_swizzle) {
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*segment_order_horz = segment_order__na;
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*segment_order_vert = segment_order__contiguous;
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return true;
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}
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if (bytes_per_element == 8 && display_swizzle) {
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*segment_order_horz = segment_order__contiguous;
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*segment_order_vert = segment_order__non_contiguous;
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return true;
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}
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return false;
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}
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static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
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unsigned int bytes_per_element)
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{
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/* copied from DML. might want to refactor DML to leverage from DML */
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/* DML : get_blk256_size */
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if (bytes_per_element == 1) {
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*blk256_width = 16;
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*blk256_height = 16;
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} else if (bytes_per_element == 2) {
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*blk256_width = 16;
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*blk256_height = 8;
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} else if (bytes_per_element == 4) {
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*blk256_width = 8;
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*blk256_height = 8;
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} else if (bytes_per_element == 8) {
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*blk256_width = 8;
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*blk256_height = 4;
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}
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}
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static void det_request_size(
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unsigned int height,
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unsigned int width,
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unsigned int bpe,
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bool *req128_horz_wc,
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bool *req128_vert_wc)
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{
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unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
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unsigned int blk256_height = 0;
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unsigned int blk256_width = 0;
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unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
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get_blk256_size(&blk256_width, &blk256_height, bpe);
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swath_bytes_horz_wc = height * blk256_height * bpe;
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swath_bytes_vert_wc = width * blk256_width * bpe;
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*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
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false : /* full 256B request */
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true; /* half 128b request */
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*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
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false : /* full 256B request */
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true; /* half 128b request */
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}
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static bool get_dcc_compression_cap(const struct dc *dc,
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static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
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const struct dc_dcc_surface_param *input,
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struct dc_surface_dcc_cap *output)
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{
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/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
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enum dcc_control dcc_control;
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unsigned int bpe;
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enum segment_order segment_order_horz, segment_order_vert;
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bool req128_horz_wc, req128_vert_wc;
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memset(output, 0, sizeof(*output));
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if (dc->debug.disable_dcc == DCC_DISABLE)
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return false;
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if (!dcc_support_pixel_format(input->format,
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&bpe))
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return false;
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if (!dcc_support_swizzle(input->swizzle_mode, bpe,
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&segment_order_horz, &segment_order_vert))
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return false;
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det_request_size(input->surface_size.height, input->surface_size.width,
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bpe, &req128_horz_wc, &req128_vert_wc);
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if (!req128_horz_wc && !req128_vert_wc) {
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dcc_control = dcc_control__256_256_xxx;
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} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
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if (!req128_horz_wc)
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dcc_control = dcc_control__256_256_xxx;
|
||||
else if (segment_order_horz == segment_order__contiguous)
|
||||
dcc_control = dcc_control__128_128_xxx;
|
||||
else
|
||||
dcc_control = dcc_control__256_64_64;
|
||||
} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
|
||||
if (!req128_vert_wc)
|
||||
dcc_control = dcc_control__256_256_xxx;
|
||||
else if (segment_order_vert == segment_order__contiguous)
|
||||
dcc_control = dcc_control__128_128_xxx;
|
||||
else
|
||||
dcc_control = dcc_control__256_64_64;
|
||||
} else {
|
||||
if ((req128_horz_wc &&
|
||||
segment_order_horz == segment_order__non_contiguous) ||
|
||||
(req128_vert_wc &&
|
||||
segment_order_vert == segment_order__non_contiguous))
|
||||
/* access_dir not known, must use most constraining */
|
||||
dcc_control = dcc_control__256_64_64;
|
||||
else
|
||||
/* reg128 is true for either horz and vert
|
||||
* but segment_order is contiguous
|
||||
*/
|
||||
dcc_control = dcc_control__128_128_xxx;
|
||||
}
|
||||
|
||||
if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
|
||||
dcc_control != dcc_control__256_256_xxx)
|
||||
return false;
|
||||
|
||||
switch (dcc_control) {
|
||||
case dcc_control__256_256_xxx:
|
||||
output->grph.rgb.max_uncompressed_blk_size = 256;
|
||||
output->grph.rgb.max_compressed_blk_size = 256;
|
||||
output->grph.rgb.independent_64b_blks = false;
|
||||
break;
|
||||
case dcc_control__128_128_xxx:
|
||||
output->grph.rgb.max_uncompressed_blk_size = 128;
|
||||
output->grph.rgb.max_compressed_blk_size = 128;
|
||||
output->grph.rgb.independent_64b_blks = false;
|
||||
break;
|
||||
case dcc_control__256_64_64:
|
||||
output->grph.rgb.max_uncompressed_blk_size = 256;
|
||||
output->grph.rgb.max_compressed_blk_size = 64;
|
||||
output->grph.rgb.independent_64b_blks = true;
|
||||
break;
|
||||
}
|
||||
|
||||
output->capable = true;
|
||||
output->const_color_support = false;
|
||||
|
||||
return true;
|
||||
return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
|
||||
dc->res_pool->hubbub,
|
||||
input,
|
||||
output);
|
||||
}
|
||||
|
||||
|
||||
static void dcn10_destroy_resource_pool(struct resource_pool **pool)
|
||||
{
|
||||
struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
|
||||
@ -1186,7 +967,7 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st
|
||||
}
|
||||
|
||||
static struct dc_cap_funcs cap_funcs = {
|
||||
.get_dcc_compression_cap = get_dcc_compression_cap
|
||||
.get_dcc_compression_cap = dcn10_get_dcc_compression_cap
|
||||
};
|
||||
|
||||
static struct resource_funcs dcn10_res_pool_funcs = {
|
||||
|
||||
64
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
Normal file
64
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
Normal file
@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright 2012-15 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DAL_DCHUBBUB_H__
|
||||
#define __DAL_DCHUBBUB_H__
|
||||
|
||||
|
||||
enum dcc_control {
|
||||
dcc_control__256_256_xxx,
|
||||
dcc_control__128_128_xxx,
|
||||
dcc_control__256_64_64,
|
||||
};
|
||||
|
||||
enum segment_order {
|
||||
segment_order__na,
|
||||
segment_order__contiguous,
|
||||
segment_order__non_contiguous,
|
||||
};
|
||||
|
||||
|
||||
struct hubbub_funcs {
|
||||
void (*update_dchub)(
|
||||
struct hubbub *hubbub,
|
||||
struct dchub_init_data *dh_data);
|
||||
|
||||
bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
|
||||
const struct dc_dcc_surface_param *input,
|
||||
struct dc_surface_dcc_cap *output);
|
||||
|
||||
bool (*dcc_support_swizzle)(
|
||||
enum swizzle_mode_values swizzle,
|
||||
unsigned int bytes_per_element,
|
||||
enum segment_order *segment_order_horz,
|
||||
enum segment_order *segment_order_vert);
|
||||
|
||||
bool (*dcc_support_pixel_format)(
|
||||
enum surface_pixel_format format,
|
||||
unsigned int *bytes_per_element);
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user