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Devicetree fixes for v5.18, take 1:

Browse Source 
- Clean-up missing '/schemas' in $ref paths
 
 - Fix MediaTek Vcodec decoder example 'dma-ranges' errors
 
 - Expand available values of PBL for snps,dwmac to fix warnings in
   mediatek-dwmac.yaml example
 
 - Fix warnings in MediaTek display bindings
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Merge tag 'devicetree-fixes-for-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree fixes from Rob Herring:

 - Clean-up missing '/schemas' in $ref paths

 - Fix MediaTek Vcodec decoder example 'dma-ranges' errors

 - Expand available values of PBL for snps,dwmac to fix warnings in
   mediatek-dwmac.yaml example

 - Fix warnings in MediaTek display bindings

* tag 'devicetree-fixes-for-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  dt-bindings: Fix missing '/schemas' in $ref paths
  dt-bindings: media: mediatek,vcodec: Fix addressing cell sizes
  dt-bindings: net: snps,dwmac: modify available values of PBL
  dt-bindings: display: mediatek: Fix examples on new bindings
  dt-bindings: display: mediatek, ovl: Fix 'iommu' required property typo
  dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type
  Revert "dt-bindings: display: mediatek: add ethdr definition for mt8195"
This commit is contained in:
Linus Torvalds 2022-03-29 08:55:16 -07:00
commit 5efabdadcf
28 changed files with 336 additions and 351 deletions
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2
Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml
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@ -42,7 +42,7 @@ patternProperties:
description:
The individual power management domains within this controller
type: object
$ref: /power/apple,pmgr-pwrstate.yaml#
$ref: /schemas/power/apple,pmgr-pwrstate.yaml#
required:
- compatible

23
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
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@ -66,12 +66,21 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
aal@14015000 {
compatible = "mediatek,mt8173-disp-aal";
reg = <0 0x14015000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_AAL>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
aal@14015000 {
compatible = "mediatek,mt8173-disp-aal";
reg = <0 0x14015000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_AAL>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
};
};

23
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
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@ -65,12 +65,21 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/gce/mt8183-gce.h>
ccorr0: ccorr@1400f000 {
compatible = "mediatek,mt8183-disp-ccorr";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
ccorr0: ccorr@1400f000 {
compatible = "mediatek,mt8183-disp-ccorr";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
};
};

23
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
View File

@ -75,12 +75,21 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
color0: color@14013000 {
compatible = "mediatek,mt8173-disp-color";
reg = <0 0x14013000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
color0: color@14013000 {
compatible = "mediatek,mt8173-disp-color";
reg = <0 0x14013000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
};
};

23
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
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@ -65,12 +65,21 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/gce/mt8183-gce.h>
dither0: dither@14012000 {
compatible = "mediatek,mt8183-disp-dither";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
dither0: dither@14012000 {
compatible = "mediatek,mt8183-disp-dither";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
};
};

3
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
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@ -70,8 +70,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;

23
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
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@ -60,12 +60,21 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/gce/mt8195-gce.h>
dsc0: disp_dsc_wrap@1c009000 {
compatible = "mediatek,mt8195-disp-dsc";
reg = <0 0x1c009000 0 0x1000>;
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
dsc0: disp_dsc_wrap@1c009000 {
compatible = "mediatek,mt8195-disp-dsc";
reg = <0 0x1c009000 0 0x1000>;
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
};
};

147
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
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@ -1,147 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Ethdr Device Tree Bindings
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
description: |
ETHDR is designed for HDR video and graphics conversion in the external display path.
It handles multiple HDR input types and performs tone mapping, color space/color
format conversion, and then combine different layers, output the required HDR or
SDR signal to the subsequent display path. This engine is composed of two video
frontends, two graphic frontends, one video backend and a mixer. ETHDR has two
DMA function blocks, DS and ADL. These two function blocks read the pre-programmed
registers from DRAM and set them to HW in the v-blanking period.
properties:
compatible:
items:
- const: mediatek,mt8195-disp-ethdr
reg:
maxItems: 7
reg-names:
items:
- const: mixer
- const: vdo_fe0
- const: vdo_fe1
- const: gfx_fe0
- const: gfx_fe1
- const: vdo_be
- const: adl_ds
interrupts:
minItems: 1
iommus:
description: The compatible property is DMA function blocks.
Should point to the respective IOMMU block with master port as argument,
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
details.
minItems: 1
maxItems: 2
clocks:
items:
- description: mixer clock
- description: video frontend 0 clock
- description: video frontend 1 clock
- description: graphic frontend 0 clock
- description: graphic frontend 1 clock
- description: video backend clock
- description: autodownload and menuload clock
- description: video frontend 0 async clock
- description: video frontend 1 async clock
- description: graphic frontend 0 async clock
- description: graphic frontend 1 async clock
- description: video backend async clock
- description: ethdr top clock
clock-names:
items:
- const: mixer
- const: vdo_fe0
- const: vdo_fe1
- const: gfx_fe0
- const: gfx_fe1
- const: vdo_be
- const: adl_ds
- const: vdo_fe0_async
- const: vdo_fe1_async
- const: gfx_fe0_async
- const: gfx_fe1_async
- const: vdo_be_async
- const: ethdr_top
power-domains:
maxItems: 1
resets:
maxItems: 5
mediatek,gce-client-reg:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: The register of display function block to be set by gce.
There are 4 arguments in this property, gce node, subsys id, offset and
register size. The subsys id is defined in the gce header of each chips
include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
display function block.
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- power-domains
additionalProperties: false
examples:
- |
disp_ethdr@1c114000 {
compatible = "mediatek,mt8195-disp-ethdr";
reg = <0 0x1c114000 0 0x1000>,
<0 0x1c115000 0 0x1000>,
<0 0x1c117000 0 0x1000>,
<0 0x1c119000 0 0x1000>,
<0 0x1c11A000 0 0x1000>,
<0 0x1c11B000 0 0x1000>,
<0 0x1c11C000 0 0x1000>;
reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
"vdo_be", "adl_ds";
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
<&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
<&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
<&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
<&gce0 SUBSYS_1c11XXXX 0xA000 0x1000>,
<&gce0 SUBSYS_1c11XXXX 0xB000 0x1000>,
<&gce0 SUBSYS_1c11XXXX 0xC000 0x1000>;
clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
<&vdosys1 CLK_VDO1_HDR_VDO_BE>,
<&vdosys1 CLK_VDO1_26M_SLOW>,
<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
<&topckgen CLK_TOP_ETHDR_SEL>;
clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
"vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
"gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
"ethdr_top";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
<&iommu_vpp M4U_PORT_L3_HDR_ADL>;
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
...

23
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
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@ -66,12 +66,21 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
gamma@14016000 {
compatible = "mediatek,mt8173-disp-gamma";
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
gamma@14016000 {
compatible = "mediatek,mt8173-disp-gamma";
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
};
};

47
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
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@ -38,18 +38,16 @@ properties:
Documentation/devicetree/bindings/power/power-domain.yaml for details.
clocks:
minItems: 1
maxItems: 2
items:
- description: MERGE Clock
- description: MERGE Async Clock
Controlling the synchronous process between MERGE and other display
function blocks cross clock domain.
clock-names:
maxItems: 2
items:
- const: merge
- const: merge_async
oneOf:
- items:
- const: merge
- items:
- const: merge
- const: merge_async
mediatek,merge-fifo-en:
description:
@ -88,23 +86,20 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
merge@14017000 {
compatible = "mediatek,mt8173-disp-merge";
reg = <0 0x14017000 0 0x1000>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_MERGE>;
soc {
#address-cells = <2>;
#size-cells = <2>;
merge@14017000 {
compatible = "mediatek,mt8173-disp-merge";
reg = <0 0x14017000 0 0x1000>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_MERGE>;
clock-names = "merge";
};
};
merge5: disp_vpp_merge5@1c110000 {
compatible = "mediatek,mt8195-disp-merge";
reg = <0 0x1c110000 0 0x1000>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
<&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
clock-names = "merge","merge_async";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
mediatek,merge-fifo-en = <1>;
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
};

27
Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
View File

@ -58,7 +58,7 @@ properties:
The event id which is mapping to the specific hardware event signal
to gce. The event id is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
$ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
@ -71,13 +71,22 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
mutex: mutex@14020000 {
compatible = "mediatek,mt8173-disp-mutex";
reg = <0 0x14020000 0 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_MUTEX_32K>;
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
soc {
#address-cells = <2>;
#size-cells = <2>;
mutex: mutex@14020000 {
compatible = "mediatek,mt8173-disp-mutex";
reg = <0 0x14020000 0 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_MUTEX_32K>;
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
};
};

14
Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
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@ -45,9 +45,15 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
od@14023000 {
compatible = "mediatek,mt8173-disp-od";
reg = <0 0x14023000 0 0x1000>;
clocks = <&mmsys CLK_MM_DISP_OD>;
soc {
#address-cells = <2>;
#size-cells = <2>;
od@14023000 {
compatible = "mediatek,mt8173-disp-od";
reg = <0 0x14023000 0 0x1000>;
clocks = <&mmsys CLK_MM_DISP_OD>;
};
};

26
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
View File

@ -66,13 +66,23 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/gce/mt8183-gce.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
ovl_2l0: ovl@14009000 {
compatible = "mediatek,mt8183-disp-ovl-2l";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
ovl_2l0: ovl@14009000 {
compatible = "mediatek,mt8183-disp-ovl-2l";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
};

28
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
View File

@ -75,19 +75,29 @@ required:
- interrupts
- power-domains
- clocks
- iommu
- iommus
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
ovl0: ovl@1400c000 {
compatible = "mediatek,mt8173-disp-ovl";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
ovl0: ovl@1400c000 {
compatible = "mediatek,mt8173-disp-ovl";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
};

23
Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
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@ -58,12 +58,21 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/power/mt8192-power.h>
#include <dt-bindings/gce/mt8192-gce.h>
postmask0: postmask@1400d000 {
compatible = "mediatek,mt8192-disp-postmask";
reg = <0 0x1400d000 0 0x1000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
postmask0: postmask@1400d000 {
compatible = "mediatek,mt8192-disp-postmask";
reg = <0 0x1400d000 0 0x1000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
};

28
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
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@ -94,14 +94,24 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
rdma0: rdma@1400e000 {
compatible = "mediatek,mt8173-disp-rdma";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,rdma-fifosize = <8192>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
rdma0: rdma@1400e000 {
compatible = "mediatek,mt8173-disp-rdma";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,rdma-fifo-size = <8192>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
};

17
Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
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@ -49,10 +49,17 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
split0: split@14018000 {
compatible = "mediatek,mt8173-disp-split";
reg = <0 0x14018000 0 0x1000>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
soc {
#address-cells = <2>;
#size-cells = <2>;
split0: split@14018000 {
compatible = "mediatek,mt8173-disp-split";
reg = <0 0x14018000 0 0x1000>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
};
};

19
Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
View File

@ -51,11 +51,18 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
ufoe@1401a000 {
compatible = "mediatek,mt8173-disp-ufoe";
reg = <0 0x1401a000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_UFOE>;
ufoe@1401a000 {
compatible = "mediatek,mt8173-disp-ufoe";
reg = <0 0x1401a000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_UFOE>;
};
};

26
Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
View File

@ -64,13 +64,23 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
wdma0: wdma@14011000 {
compatible = "mediatek,mt8173-disp-wdma";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
soc {
#address-cells = <2>;
#size-cells = <2>;
wdma0: wdma@14011000 {
compatible = "mediatek,mt8173-disp-wdma";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
};
};

120
Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
View File

@ -72,10 +72,10 @@ properties:
Describes the physical address space of IOMMU maps to memory.
"#address-cells":
const: 1
const: 2
"#size-cells":
const: 1
const: 2
ranges: true
@ -205,61 +205,67 @@ examples:
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/power/mt8192-power.h>
video-codec@16000000 {
compatible = "mediatek,mt8192-vcodec-dec";
mediatek,scp = <&scp>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x16000000 0x40000>;
reg = <0x16000000 0x1000>; /* VDEC_SYS */
vcodec-lat@10000 {
compatible = "mediatek,mtk-vcodec-lat";
reg = <0x10000 0x800>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
};
bus@16000000 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0x16000000 0x16000000 0 0x40000>;
vcodec-core@25000 {
compatible = "mediatek,mtk-vcodec-core";
reg = <0x25000 0x1000>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
<&vdecsys CLK_VDEC_VDEC>,
<&vdecsys CLK_VDEC_LAT>,
<&vdecsys CLK_VDEC_LARB1>,
<&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
video-codec@16000000 {
compatible = "mediatek,mt8192-vcodec-dec";
mediatek,scp = <&scp>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0x16000000 0 0x40000>;
reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
vcodec-lat@10000 {
compatible = "mediatek,mtk-vcodec-lat";
reg = <0 0x10000 0 0x800>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
};
vcodec-core@25000 {
compatible = "mediatek,mtk-vcodec-core";
reg = <0 0x25000 0 0x1000>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
<&vdecsys CLK_VDEC_VDEC>,
<&vdecsys CLK_VDEC_LAT>,
<&vdecsys CLK_VDEC_LARB1>,
<&topckgen CLK_TOP_MAINPLL_D4>;
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
};
};
};

2
Documentation/devicetree/bindings/net/dsa/dsa-port.yaml
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@ -15,7 +15,7 @@ description:
Ethernet switch port Description
allOf:
- $ref: "http://devicetree.org/schemas/net/ethernet-controller.yaml#"
- $ref: /schemas/net/ethernet-controller.yaml#
properties:
reg:

6
Documentation/devicetree/bindings/net/snps,dwmac.yaml
View File

@ -340,21 +340,21 @@ allOf:
description:
Programmable Burst Length (tx and rx)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 8]
enum: [1, 2, 4, 8, 16, 32]
snps,txpbl:
description:
Tx Programmable Burst Length. If set, DMA tx will use this
value rather than snps,pbl.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 8]
enum: [1, 2, 4, 8, 16, 32]
snps,rxpbl:
description:
Rx Programmable Burst Length. If set, DMA rx will use this
value rather than snps,pbl.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 8]
enum: [1, 2, 4, 8, 16, 32]
snps,no-pbl-x8:
$ref: /schemas/types.yaml#/definitions/flag

2
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
View File

@ -103,7 +103,7 @@ patternProperties:
supports up to 50MHz, up to four chip selects, programmable
data path from 4 bits to 32 bits and numerous protocol
variants.
$ref: /spi/spi-controller.yaml#
$ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:

2
Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
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@ -18,7 +18,7 @@ description: |
capability of this controller.
allOf:
- $ref: /spi/spi-controller.yaml#
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:

2
Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
View File

@ -16,7 +16,7 @@ description: The QSPI controller allows SPI protocol communication in single,
as NOR flash.
allOf:
- $ref: /spi/spi-controller.yaml#
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:

2
Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml
View File

@ -44,7 +44,7 @@ description: |
compatibility.
allOf:
- $ref: /spi/spi-controller.yaml#
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:

4
Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
View File

@ -132,7 +132,7 @@ properties:
default: host
connector:
$ref: /connector/usb-connector.yaml#
$ref: /schemas/connector/usb-connector.yaml#
description:
Connector for dual role switch, especially for "gpio-usb-b-connector"
type: object
@ -191,7 +191,7 @@ properties:
patternProperties:
"^usb@[0-9a-f]+$":
type: object
$ref: /usb/mediatek,mtk-xhci.yaml#
$ref: /schemas/usb/mediatek,mtk-xhci.yaml#
description:
The xhci should be added as subnode to mtu3 as shown in the following
example if the host mode is enabled.

2
Documentation/devicetree/bindings/usb/mediatek,musb.yaml
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@ -63,7 +63,7 @@ properties:
maxItems: 1
connector:
$ref: /connector/usb-connector.yaml#
$ref: /schemas/connector/usb-connector.yaml#
description: Connector for dual role switch
type: object