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drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga

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This patch enables clock gating for the UVD5 block with
Tonga.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom St Denis 2016-03-23 13:16:13 -04:00 committed by Alex Deucher
parent be3ecca7fe
commit 5f64e77e47
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/amdgpu/vi.c
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@ -1081,7 +1081,7 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x3c;
break;
case CHIP_TONGA:
adev->cg_flags = 0;
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x14;
break;