net/mlx4_en: Remove RX buffers alignment to IP_ALIGN
When IP_ALIGN has a non zero value, hardware will write to a non aligned address. The only reader from this address is when copying the header from the first frag into the linear buffer (further access to the IP address will be from the linear buffer, in which the headers are aligned). Since the penalty of non align access by the hardware is greater than the software memcpy, changing the frag_align to always be 0. Signed-off-by: Ido Shamay <idos@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -74,7 +74,7 @@ static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
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page_alloc->page_size = PAGE_SIZE << order;
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page_alloc->page = page;
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page_alloc->dma = dma;
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page_alloc->page_offset = frag_info->frag_align;
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page_alloc->page_offset = 0;
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/* Not doing get_page() for each frag is a big win
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* on asymetric workloads. Note we can not use atomic_set().
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*/
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@ -945,15 +945,8 @@ void mlx4_en_calc_rx_buf(struct net_device *dev)
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(eff_mtu > buf_size + frag_sizes[i]) ?
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frag_sizes[i] : eff_mtu - buf_size;
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priv->frag_info[i].frag_prefix_size = buf_size;
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if (!i) {
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priv->frag_info[i].frag_align = NET_IP_ALIGN;
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priv->frag_info[i].frag_stride =
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ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
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} else {
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priv->frag_info[i].frag_align = 0;
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priv->frag_info[i].frag_stride =
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ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
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}
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priv->frag_info[i].frag_stride = ALIGN(frag_sizes[i],
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SMP_CACHE_BYTES);
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buf_size += priv->frag_info[i].frag_size;
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i++;
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}
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@ -966,11 +959,10 @@ void mlx4_en_calc_rx_buf(struct net_device *dev)
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eff_mtu, priv->num_frags);
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for (i = 0; i < priv->num_frags; i++) {
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en_err(priv,
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" frag:%d - size:%d prefix:%d align:%d stride:%d\n",
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" frag:%d - size:%d prefix:%d stride:%d\n",
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i,
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priv->frag_info[i].frag_size,
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priv->frag_info[i].frag_prefix_size,
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priv->frag_info[i].frag_align,
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priv->frag_info[i].frag_stride);
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}
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}
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@ -481,7 +481,6 @@ struct mlx4_en_frag_info {
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u16 frag_size;
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u16 frag_prefix_size;
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u16 frag_stride;
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u16 frag_align;
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};
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#ifdef CONFIG_MLX4_EN_DCB
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