arm64: dts: qcom: Add SM6350 device tree
Add a base DT for SM6350 SoC Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210923162204.21752-2-konrad.dybcio@somainline.org
This commit is contained in:
Konrad Dybcio
Bjorn Andersson
parent
55d0feb3ab
commit
5f82b9cda6
485
arch/arm64/boot/dts/qcom/sm6350.dtsi
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485
arch/arm64/boot/dts/qcom/sm6350.dtsi
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@ -0,0 +1,485 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32764>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo560";
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reg = <0x0 0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo560";
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reg = <0x0 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_100>;
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#cooling-cells = <2>;
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L2_100: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo560";
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reg = <0x0 0x200>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_200>;
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#cooling-cells = <2>;
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L2_200: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo560";
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reg = <0x0 0x300>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_300>;
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#cooling-cells = <2>;
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L2_300: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo560";
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reg = <0x0 0x400>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_400>;
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#cooling-cells = <2>;
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L2_400: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo560";
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reg = <0x0 0x500>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_500>;
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#cooling-cells = <2>;
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L2_500: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo560";
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reg = <0x0 0x600>;
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enable-method = "psci";
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <703>;
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next-level-cache = <&L2_600>;
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo560";
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reg = <0x0 0x700>;
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enable-method = "psci";
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <703>;
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next-level-cache = <&L2_700>;
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#cooling-cells = <2>;
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L2_700: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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firmware {
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scm: scm {
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compatible = "qcom,scm-sm6350", "qcom,scm";
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#reset-cells = <1>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: memory@80000000 {
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reg = <0 0x80000000 0 0x600000>;
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no-map;
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};
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xbl_aop_mem: memory@80700000 {
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reg = <0 0x80700000 0 0x160000>;
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no-map;
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};
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cmd_db: memory@80860000 {
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compatible = "qcom,cmd-db";
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reg = <0 0x80860000 0 0x20000>;
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no-map;
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};
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sec_apps_mem: memory@808ff000 {
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reg = <0 0x808ff000 0 0x1000>;
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no-map;
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};
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smem_mem: memory@80900000 {
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reg = <0 0x80900000 0 0x200000>;
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no-map;
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};
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cdsp_sec_mem: memory@80b00000 {
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reg = <0 0x80b00000 0 0x1e00000>;
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no-map;
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};
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pil_camera_mem: memory@86000000 {
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reg = <0 0x86000000 0 0x500000>;
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no-map;
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};
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pil_npu_mem: memory@86500000 {
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reg = <0 0x86500000 0 0x500000>;
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no-map;
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};
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pil_video_mem: memory@86a00000 {
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reg = <0 0x86a00000 0 0x500000>;
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no-map;
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};
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pil_cdsp_mem: memory@86f00000 {
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reg = <0 0x86f00000 0 0x1e00000>;
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no-map;
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};
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pil_adsp_mem: memory@88d00000 {
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reg = <0 0x88d00000 0 0x2800000>;
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no-map;
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};
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wlan_fw_mem: memory@8b500000 {
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reg = <0 0x8b500000 0 0x200000>;
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no-map;
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};
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pil_ipa_fw_mem: memory@8b700000 {
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reg = <0 0x8b700000 0 0x10000>;
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no-map;
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};
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pil_ipa_gsi_mem: memory@8b710000 {
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reg = <0 0x8b710000 0 0x5400>;
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no-map;
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};
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pil_gpu_mem: memory@8b715400 {
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reg = <0 0x8b715400 0 0x2000>;
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no-map;
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};
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pil_modem_mem: memory@8b800000 {
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reg = <0 0x8b800000 0 0xf800000>;
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no-map;
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};
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cont_splash_memory: memory@a0000000 {
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reg = <0 0xa0000000 0 0x2300000>;
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no-map;
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};
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dfps_data_memory: memory@a2300000 {
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reg = <0 0xa2300000 0 0x100000>;
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no-map;
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};
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removed_region: memory@c0000000 {
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reg = <0 0xc0000000 0 0x3900000>;
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no-map;
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};
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debug_region: memory@ffb00000 {
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reg = <0 0xffb00000 0 0xc0000>;
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no-map;
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};
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last_log_region: memory@ffbc0000 {
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reg = <0 0xffbc0000 0 0x40000>;
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no-map;
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};
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ramoops: ramoops@ffc00000 {
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compatible = "removed-dma-pool", "ramoops";
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reg = <0 0xffc00000 0 0x00100000>;
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record-size = <0x1000>;
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console-size = <0x40000>;
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ftrace-size = <0x0>;
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msg-size = <0x20000 0x20000>;
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cc-size = <0x0>;
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no-map;
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};
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cmdline_region: memory@ffd00000 {
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reg = <0 0xffd00000 0 0x1000>;
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no-map;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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dma-ranges = <0 0 0 0 0x10 0>;
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compatible = "simple-bus";
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ipcc: mailbox@408000 {
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compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
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reg = <0 0x00408000 0 0x1000>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01f40000 0x0 0x40000>;
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#hwlock-cells = <1>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm6350-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
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qcom,pdc-ranges = <0 480 94>, <94 609 31>,
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<125 63 1>, <126 655 12>, <138 139 15>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
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<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog@17c10000 {
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compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
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reg = <0 0x17c10000 0 0x1000>;
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clocks = <&sleep_clk>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer@17c20000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x17c20000 0x0 0x1000>;
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clock-frequency = <19200000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c21000 0x0 0x1000>,
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<0x0 0x17c22000 0x0 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c23000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c25000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c27000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c29000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c2b000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c2d000 0x0 0x1000>;
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status = "disabled";
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};
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};
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apps_rsc: rsc@18200000 {
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compatible = "qcom,rpmh-rsc";
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label = "apps_rsc";
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reg = <0x0 0x18200000 0x0 0x10000>,
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<0x0 0x18210000 0x0 0x10000>,
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<0x0 0x18220000 0x0 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
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<WAKE_TCS 3>, <CONTROL_TCS 1>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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clock-frequency = <19200000>;
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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