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clk: microchip: mpfs: simplify control reg access

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The control reg addresses are known when the clocks are registered, so
we can, instead of assigning a base pointer to the structs, assign the
control reg addresses directly. Accordingly, remove the interim
variables used during reads/writes to those registers.

Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-11-conor.dooley@microchip.com
This commit is contained in:
Conor Dooley 2022-09-09 13:31:19 +01:00 committed by Claudiu Beznea
parent 52fe6b5293
commit 5fa27b77a1
1 changed files with 17 additions and 25 deletions
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42
drivers/clk/microchip/clk-mpfs.c
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@ -50,6 +50,7 @@ struct mpfs_msspll_hw_clock {
#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
struct mpfs_cfg_clock {
void __iomem *reg;
const struct clk_div_table *table;
u8 shift;
u8 width;
@ -58,7 +59,6 @@ struct mpfs_cfg_clock {
struct mpfs_cfg_hw_clock {
struct mpfs_cfg_clock cfg;
void __iomem *sys_base;
struct clk_hw hw;
struct clk_init_data init;
unsigned int id;
@ -68,12 +68,12 @@ struct mpfs_cfg_hw_clock {
#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
struct mpfs_periph_clock {
void __iomem *reg;
u8 shift;
};
struct mpfs_periph_hw_clock {
struct mpfs_periph_clock periph;
void __iomem *sys_base;
struct clk_hw hw;
unsigned int id;
};
@ -212,14 +212,13 @@ static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_cl
static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
unsigned int num_clks, struct mpfs_clock_data *data)
{
void __iomem *base = data->msspll_base;
unsigned int i;
int ret;
for (i = 0; i < num_clks; i++) {
struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
ret = mpfs_clk_register_msspll(dev, msspll_hw, base);
ret = mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base);
if (ret)
return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
CLK_MSSPLL);
@ -238,10 +237,9 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
void __iomem *base_addr = cfg_hw->sys_base;
u32 val;
val = readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift;
val = readl_relaxed(cfg->reg) >> cfg->shift;
val &= clk_div_mask(cfg->width);
return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
@ -259,7 +257,6 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
void __iomem *base_addr = cfg_hw->sys_base;
unsigned long flags;
u32 val;
int divider_setting;
@ -270,10 +267,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned
return divider_setting;
spin_lock_irqsave(&mpfs_clk_lock, flags);
val = readl_relaxed(base_addr + cfg_hw->reg_offset);
val = readl_relaxed(cfg->reg);
val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
val |= divider_setting << cfg->shift;
writel_relaxed(val, base_addr + cfg_hw->reg_offset);
writel_relaxed(val, cfg->reg);
spin_unlock_irqrestore(&mpfs_clk_lock, flags);
@ -321,9 +318,9 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
};
static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw,
void __iomem *sys_base)
void __iomem *base)
{
cfg_hw->sys_base = sys_base;
cfg_hw->cfg.reg = base + cfg_hw->reg_offset;
return devm_clk_hw_register(dev, &cfg_hw->hw);
}
@ -331,14 +328,13 @@ static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *c
static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
unsigned int num_clks, struct mpfs_clock_data *data)
{
void __iomem *sys_base = data->base;
unsigned int i, id;
int ret;
for (i = 0; i < num_clks; i++) {
struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base);
ret = mpfs_clk_register_cfg(dev, cfg_hw, data->base);
if (ret)
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
cfg_hw->id);
@ -358,15 +354,14 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw)
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
void __iomem *base_addr = periph_hw->sys_base;
u32 reg, val;
unsigned long flags;
spin_lock_irqsave(&mpfs_clk_lock, flags);
reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
reg = readl_relaxed(periph->reg);
val = reg | (1u << periph->shift);
writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
writel_relaxed(val, periph->reg);
spin_unlock_irqrestore(&mpfs_clk_lock, flags);
@ -377,15 +372,14 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw)
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
void __iomem *base_addr = periph_hw->sys_base;
u32 reg, val;
unsigned long flags;
spin_lock_irqsave(&mpfs_clk_lock, flags);
reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
reg = readl_relaxed(periph->reg);
val = reg & ~(1u << periph->shift);
writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
writel_relaxed(val, periph->reg);
spin_unlock_irqrestore(&mpfs_clk_lock, flags);
}
@ -394,10 +388,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
void __iomem *base_addr = periph_hw->sys_base;
u32 reg;
reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
reg = readl_relaxed(periph->reg);
if (reg & (1u << periph->shift))
return 1;
@ -466,9 +459,9 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
};
static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw,
void __iomem *sys_base)
void __iomem *base)
{
periph_hw->sys_base = sys_base;
periph_hw->periph.reg = base + REG_SUBBLK_CLOCK_CR;
return devm_clk_hw_register(dev, &periph_hw->hw);
}
@ -476,14 +469,13 @@ static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_cl
static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
int num_clks, struct mpfs_clock_data *data)
{
void __iomem *sys_base = data->base;
unsigned int i, id;
int ret;
for (i = 0; i < num_clks; i++) {
struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
ret = mpfs_clk_register_periph(dev, periph_hw, sys_base);
ret = mpfs_clk_register_periph(dev, periph_hw, data->base);
if (ret)
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
periph_hw->id);