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drm/radeon: apply more strict limits for PLL params v2

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Letting post and refernce divider get to big is bad for signal stability.

v2: increase the limit to 210

Signed-off-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
Christian König 2014-04-04 13:45:42 +02:00
parent 6abc6d5c73
commit 5fb9cc4d8b
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/radeon/radeon_display.c
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@ -937,6 +937,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
} }
post_div = post_div_best; post_div = post_div_best;
/* limit reference * post divider to a maximum */
ref_div_max = min(210 / post_div, ref_div_max);
/* get matching reference and feedback divider */ /* get matching reference and feedback divider */
ref_div = max(den / post_div, 1u); ref_div = max(den / post_div, 1u);
fb_div = nom; fb_div = nom;