ixgbe: Remove driver config for KX4 PHY
The KX4 PHY is configured by the NVM. Currently, the driver is overwriting the config; remove the code associated with KX4 configuration. Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Tested-by: Krishneil Singh <krishneil.k.singh@intel.com>
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@ -792,7 +792,8 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
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hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
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/* Setup link based on the new speed settings */
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hw->phy.ops.setup_link(hw);
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if (hw->phy.ops.setup_link)
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hw->phy.ops.setup_link(hw);
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return 0;
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}
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@ -3754,15 +3754,6 @@ struct ixgbe_info {
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#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN BIT(3)
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#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN BIT(31)
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#define IXGBE_KX4_LINK_CNTL_1 0x4C
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#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX BIT(16)
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#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 BIT(17)
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#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX BIT(24)
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#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 BIT(25)
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#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE BIT(29)
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#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP BIT(30)
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#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART BIT(31)
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#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
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#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
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@ -3779,9 +3770,6 @@ struct ixgbe_info {
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#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
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#define IXGBE_SB_IOSF_CTRL_BUSY BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
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#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
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#define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1
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#define IXGBE_SB_IOSF_TARGET_KX4_PCS0 2
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#define IXGBE_SB_IOSF_TARGET_KX4_PCS1 3
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#define IXGBE_NW_MNG_IF_SEL 0x00011178
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#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT BIT(1)
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@ -2473,44 +2473,6 @@ static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
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return ixgbe_restart_an_internal_phy_x550em(hw);
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}
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/** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
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* @hw: pointer to hardware structure
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*
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* Configures the integrated KX4 PHY.
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**/
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static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
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{
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s32 status;
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u32 reg_val;
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status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
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IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
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hw->bus.lan_id, ®_val);
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if (status)
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return status;
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reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
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IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
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reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
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/* Advertise 10G support. */
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if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
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reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
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/* Advertise 1G support. */
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if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
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reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
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/* Restart auto-negotiation. */
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reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
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status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
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IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
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hw->bus.lan_id, reg_val);
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return status;
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}
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/**
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* ixgbe_setup_kr_x550em - Configure the KR PHY
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* @hw: pointer to hardware structure
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@ -3134,7 +3096,7 @@ static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
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/* Set functions pointers based on phy type */
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switch (hw->phy.type) {
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case ixgbe_phy_x550em_kx4:
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phy->ops.setup_link = ixgbe_setup_kx4_x550em;
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phy->ops.setup_link = NULL;
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phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
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phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
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break;
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