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ARM: dts: uniphier: add MIO DMAC nodes

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Add MIO-DMAC (Media IO DMA Controller) nodes, and use them as
the DMA engine of SD/eMMC controllers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2018-11-28 11:42:30 +09:00
parent 072ae88ad2
commit 5fd98eb7e8
3 changed files with 44 additions and 0 deletions
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14
arch/arm/boot/dts/uniphier-ld4.dtsi
View File

@ -235,6 +235,16 @@
};
};
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
@ -246,6 +256,8 @@
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
dma-names = "rx-tx";
dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
@ -263,6 +275,8 @@
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
dma-names = "rx-tx";
dmas = <&dmac 6>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;

16
arch/arm/boot/dts/uniphier-pro4.dtsi
View File

@ -269,6 +269,16 @@
};
};
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
@ -280,6 +290,8 @@
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
dma-names = "rx-tx";
dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
@ -297,6 +309,8 @@
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
dma-names = "rx-tx";
dmas = <&dmac 5>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
@ -313,6 +327,8 @@
clocks = <&mio_clk 2>;
reset-names = "host", "bridge";
resets = <&mio_rst 2>, <&mio_rst 5>;
dma-names = "rx-tx";
dmas = <&dmac 6>;
bus-width = <4>;
cap-sd-highspeed;
};

14
arch/arm/boot/dts/uniphier-sld8.dtsi
View File

@ -239,6 +239,16 @@
};
};
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
@ -250,6 +260,8 @@
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
dma-names = "rx-tx";
dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
@ -267,6 +279,8 @@
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
dma-names = "rx-tx";
dmas = <&dmac 6>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;