Merge branch 'icc-cleanup' into icc-next
* icc-cleanup interconnect: qcom: sm8550: Remove bogus per-RSC BCMs and nodes dt-bindings: interconnect: Remove bogus interconnect nodes interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes interconnect: qcom: sa8775p: constify pointer to qcom_icc_node interconnect: qcom: sm8250: constify pointer to qcom_icc_node interconnect: qcom: sm6115: constify pointer to qcom_icc_node interconnect: qcom: sa8775p: constify pointer to qcom_icc_bcm interconnect: qcom: x1e80100: constify pointer to qcom_icc_bcm dt-bindings: interconnect: qcom,rpmh: Fix bouncing @codeaurora address interconnect: constify of_phandle_args in xlate Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov
commit
6025a81ae6
@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect
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maintainers:
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- Georgi Djakov <georgi.djakov@linaro.org>
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- Odelu Kukatla <okukatla@codeaurora.org>
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- Odelu Kukatla <quic_okukatla@quicinc.com>
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description: |
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RPMh interconnect providers support system bandwidth requirements through
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@ -343,7 +343,7 @@ EXPORT_SYMBOL_GPL(icc_std_aggregate);
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* an array of icc nodes specified in the icc_onecell_data struct when
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* registering the provider.
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*/
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struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
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struct icc_node *of_icc_xlate_onecell(const struct of_phandle_args *spec,
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void *data)
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{
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struct icc_onecell_data *icc_data = data;
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@ -368,7 +368,7 @@ EXPORT_SYMBOL_GPL(of_icc_xlate_onecell);
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* Returns a valid pointer to struct icc_node_data on success or ERR_PTR()
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* on failure.
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*/
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struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
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struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec)
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{
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struct icc_node *node = ERR_PTR(-EPROBE_DEFER);
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struct icc_node_data *data = NULL;
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@ -9,7 +9,8 @@
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#include "icc-common.h"
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struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data)
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struct icc_node_data *qcom_icc_xlate_extended(const struct of_phandle_args *spec,
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void *data)
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{
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struct icc_node_data *ndata;
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struct icc_node *node;
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@ -8,6 +8,7 @@
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#include <linux/interconnect-provider.h>
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struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data);
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struct icc_node_data *qcom_icc_xlate_extended(const struct of_phandle_args *spec,
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void *data);
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#endif
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@ -2092,11 +2092,11 @@ static struct qcom_icc_bcm bcm_sn10 = {
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.nodes = { &xs_qdss_stm },
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};
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static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
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static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
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&bcm_sn3,
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};
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static struct qcom_icc_node *aggre1_noc_nodes[] = {
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static struct qcom_icc_node * const aggre1_noc_nodes[] = {
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[MASTER_QUP_3] = &qxm_qup3,
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[MASTER_EMAC] = &xm_emac_0,
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[MASTER_EMAC_1] = &xm_emac_1,
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@ -2115,12 +2115,12 @@ static const struct qcom_icc_desc sa8775p_aggre1_noc = {
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.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
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};
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static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
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static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
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&bcm_ce0,
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&bcm_sn4,
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};
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static struct qcom_icc_node *aggre2_noc_nodes[] = {
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static struct qcom_icc_node * const aggre2_noc_nodes[] = {
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[MASTER_QDSS_BAM] = &qhm_qdss_bam,
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[MASTER_QUP_0] = &qhm_qup0,
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[MASTER_QUP_1] = &qhm_qup1,
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@ -2142,13 +2142,13 @@ static const struct qcom_icc_desc sa8775p_aggre2_noc = {
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.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
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};
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static struct qcom_icc_bcm *clk_virt_bcms[] = {
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static struct qcom_icc_bcm * const clk_virt_bcms[] = {
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&bcm_qup0,
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&bcm_qup1,
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&bcm_qup2,
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};
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static struct qcom_icc_node *clk_virt_nodes[] = {
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static struct qcom_icc_node * const clk_virt_nodes[] = {
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[MASTER_QUP_CORE_0] = &qup0_core_master,
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[MASTER_QUP_CORE_1] = &qup1_core_master,
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[MASTER_QUP_CORE_2] = &qup2_core_master,
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@ -2166,7 +2166,7 @@ static const struct qcom_icc_desc sa8775p_clk_virt = {
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.num_bcms = ARRAY_SIZE(clk_virt_bcms),
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};
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static struct qcom_icc_bcm *config_noc_bcms[] = {
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static struct qcom_icc_bcm * const config_noc_bcms[] = {
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&bcm_cn0,
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&bcm_cn1,
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&bcm_cn2,
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@ -2175,7 +2175,7 @@ static struct qcom_icc_bcm *config_noc_bcms[] = {
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&bcm_sn10,
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};
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static struct qcom_icc_node *config_noc_nodes[] = {
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static struct qcom_icc_node * const config_noc_nodes[] = {
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[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
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[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
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[SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
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@ -2271,10 +2271,10 @@ static const struct qcom_icc_desc sa8775p_config_noc = {
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.num_bcms = ARRAY_SIZE(config_noc_bcms),
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};
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static struct qcom_icc_bcm *dc_noc_bcms[] = {
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static struct qcom_icc_bcm * const dc_noc_bcms[] = {
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};
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static struct qcom_icc_node *dc_noc_nodes[] = {
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static struct qcom_icc_node * const dc_noc_nodes[] = {
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[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
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[SLAVE_LLCC_CFG] = &qhs_llcc,
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[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
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@ -2287,12 +2287,12 @@ static const struct qcom_icc_desc sa8775p_dc_noc = {
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.num_bcms = ARRAY_SIZE(dc_noc_bcms),
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};
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static struct qcom_icc_bcm *gem_noc_bcms[] = {
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static struct qcom_icc_bcm * const gem_noc_bcms[] = {
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&bcm_sh0,
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&bcm_sh2,
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};
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static struct qcom_icc_node *gem_noc_nodes[] = {
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static struct qcom_icc_node * const gem_noc_nodes[] = {
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[MASTER_GPU_TCU] = &alm_gpu_tcu,
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[MASTER_PCIE_TCU] = &alm_pcie_tcu,
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[MASTER_SYS_TCU] = &alm_sys_tcu,
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@ -2323,12 +2323,12 @@ static const struct qcom_icc_desc sa8775p_gem_noc = {
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.num_bcms = ARRAY_SIZE(gem_noc_bcms),
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};
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static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = {
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static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
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&bcm_gna0,
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&bcm_gnb0,
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};
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static struct qcom_icc_node *gpdsp_anoc_nodes[] = {
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static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
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[MASTER_DSP0] = &qxm_dsp0,
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[MASTER_DSP1] = &qxm_dsp1,
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[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
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@ -2341,11 +2341,11 @@ static const struct qcom_icc_desc sa8775p_gpdsp_anoc = {
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.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
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};
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static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
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static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
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&bcm_sn9,
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};
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static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
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static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
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[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
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[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
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[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
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@ -2364,12 +2364,12 @@ static const struct qcom_icc_desc sa8775p_lpass_ag_noc = {
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.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
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};
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static struct qcom_icc_bcm *mc_virt_bcms[] = {
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static struct qcom_icc_bcm * const mc_virt_bcms[] = {
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&bcm_acv,
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&bcm_mc0,
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};
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static struct qcom_icc_node *mc_virt_nodes[] = {
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static struct qcom_icc_node * const mc_virt_nodes[] = {
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[MASTER_LLCC] = &llcc_mc,
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[SLAVE_EBI1] = &ebi,
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};
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@ -2381,12 +2381,12 @@ static const struct qcom_icc_desc sa8775p_mc_virt = {
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.num_bcms = ARRAY_SIZE(mc_virt_bcms),
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};
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static struct qcom_icc_bcm *mmss_noc_bcms[] = {
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static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
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&bcm_mm0,
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&bcm_mm1,
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};
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static struct qcom_icc_node *mmss_noc_nodes[] = {
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static struct qcom_icc_node * const mmss_noc_nodes[] = {
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[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
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[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
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[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
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@ -2413,12 +2413,12 @@ static const struct qcom_icc_desc sa8775p_mmss_noc = {
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.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
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};
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static struct qcom_icc_bcm *nspa_noc_bcms[] = {
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static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
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&bcm_nsa0,
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&bcm_nsa1,
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};
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static struct qcom_icc_node *nspa_noc_nodes[] = {
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static struct qcom_icc_node * const nspa_noc_nodes[] = {
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[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
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[MASTER_CDSP_PROC] = &qxm_nsp,
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[SLAVE_HCP_A] = &qns_hcp,
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@ -2433,12 +2433,12 @@ static const struct qcom_icc_desc sa8775p_nspa_noc = {
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.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
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};
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static struct qcom_icc_bcm *nspb_noc_bcms[] = {
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static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
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&bcm_nsb0,
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&bcm_nsb1,
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};
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static struct qcom_icc_node *nspb_noc_nodes[] = {
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static struct qcom_icc_node * const nspb_noc_nodes[] = {
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[MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
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[MASTER_CDSP_PROC_B] = &qxm_nspb,
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[SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
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@ -2453,11 +2453,11 @@ static const struct qcom_icc_desc sa8775p_nspb_noc = {
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.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
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};
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static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
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static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
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&bcm_pci0,
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};
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static struct qcom_icc_node *pcie_anoc_nodes[] = {
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static struct qcom_icc_node * const pcie_anoc_nodes[] = {
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[MASTER_PCIE_0] = &xm_pcie3_0,
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[MASTER_PCIE_1] = &xm_pcie3_1,
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[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
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@ -2470,7 +2470,7 @@ static const struct qcom_icc_desc sa8775p_pcie_anoc = {
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.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
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};
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static struct qcom_icc_bcm *system_noc_bcms[] = {
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static struct qcom_icc_bcm * const system_noc_bcms[] = {
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&bcm_sn0,
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&bcm_sn1,
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&bcm_sn3,
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@ -2478,7 +2478,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = {
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&bcm_sn9,
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};
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static struct qcom_icc_node *system_noc_nodes[] = {
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static struct qcom_icc_node * const system_noc_nodes[] = {
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[MASTER_GIC_AHB] = &qhm_gic,
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[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
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[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
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@ -1193,7 +1193,7 @@ static struct qcom_icc_node slv_anoc_snoc = {
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.links = slv_anoc_snoc_links,
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};
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static struct qcom_icc_node *bimc_nodes[] = {
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static struct qcom_icc_node * const bimc_nodes[] = {
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[MASTER_AMPSS_M0] = &apps_proc,
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[MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt,
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[MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt,
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@ -1223,7 +1223,7 @@ static const struct qcom_icc_desc sm6115_bimc = {
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.ab_coeff = 153,
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};
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static struct qcom_icc_node *config_noc_nodes[] = {
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static struct qcom_icc_node * const config_noc_nodes[] = {
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[SNOC_CNOC_MAS] = &mas_snoc_cnoc,
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[MASTER_QDSS_DAP] = &xm_dap,
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[SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb,
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@ -1294,7 +1294,7 @@ static const struct qcom_icc_desc sm6115_config_noc = {
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.keep_alive = true,
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};
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static struct qcom_icc_node *sys_noc_nodes[] = {
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static struct qcom_icc_node * const sys_noc_nodes[] = {
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[MASTER_CRYPTO_CORE0] = &crypto_c0,
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[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
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[MASTER_TIC] = &qhm_tic,
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@ -1339,7 +1339,7 @@ static const struct qcom_icc_desc sm6115_sys_noc = {
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.keep_alive = true,
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};
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static struct qcom_icc_node *clk_virt_nodes[] = {
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static struct qcom_icc_node * const clk_virt_nodes[] = {
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[MASTER_QUP_CORE_0] = &qup0_core_master,
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[SLAVE_QUP_CORE_0] = &qup0_core_slave,
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};
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@ -1353,7 +1353,7 @@ static const struct qcom_icc_desc sm6115_clk_virt = {
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.keep_alive = true,
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};
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static struct qcom_icc_node *mmnrt_virt_nodes[] = {
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static struct qcom_icc_node * const mmnrt_virt_nodes[] = {
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[MASTER_CAMNOC_SF] = &qnm_camera_nrt,
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[MASTER_VIDEO_P0] = &qxm_venus0,
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[MASTER_VIDEO_PROC] = &qxm_venus_cpu,
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@ -1370,7 +1370,7 @@ static const struct qcom_icc_desc sm6115_mmnrt_virt = {
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.ab_coeff = 142,
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};
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static struct qcom_icc_node *mmrt_virt_nodes[] = {
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static struct qcom_icc_node * const mmrt_virt_nodes[] = {
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[MASTER_CAMNOC_HF] = &qnm_camera_rt,
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[MASTER_MDP_PORT0] = &qxm_mdp0,
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[SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt,
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@ -1673,7 +1673,7 @@ static struct qcom_icc_bcm * const qup_virt_bcms[] = {
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&bcm_qup0,
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};
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static struct qcom_icc_node *qup_virt_nodes[] = {
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static struct qcom_icc_node * const qup_virt_nodes[] = {
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[MASTER_QUP_CORE_0] = &qup0_core_master,
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[MASTER_QUP_CORE_1] = &qup1_core_master,
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[MASTER_QUP_CORE_2] = &qup2_core_master,
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@ -524,231 +524,6 @@ static struct qcom_icc_node xm_gic = {
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.links = { SM8550_SLAVE_SNOC_GEM_NOC_GC },
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};
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static struct qcom_icc_node qnm_mnoc_hf_disp = {
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.name = "qnm_mnoc_hf_disp",
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.id = SM8550_MASTER_MNOC_HF_MEM_NOC_DISP,
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.channels = 2,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8550_SLAVE_LLCC_DISP },
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};
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static struct qcom_icc_node qnm_pcie_disp = {
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.name = "qnm_pcie_disp",
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.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP,
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.channels = 1,
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.buswidth = 16,
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.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node llcc_mc_disp = {
|
||||
.name = "llcc_mc_disp",
|
||||
.id = SM8550_MASTER_LLCC_DISP,
|
||||
.channels = 4,
|
||||
.buswidth = 4,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_EBI1_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mdp_disp = {
|
||||
.name = "qnm_mdp_disp",
|
||||
.id = SM8550_MASTER_MDP_DISP,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_0 = {
|
||||
.name = "qnm_mnoc_hf_cam_ife_0",
|
||||
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_0 = {
|
||||
.name = "qnm_mnoc_sf_cam_ife_0",
|
||||
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_pcie_cam_ife_0 = {
|
||||
.name = "qnm_pcie_cam_ife_0",
|
||||
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0,
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node llcc_mc_cam_ife_0 = {
|
||||
.name = "llcc_mc_cam_ife_0",
|
||||
.id = SM8550_MASTER_LLCC_CAM_IFE_0,
|
||||
.channels = 4,
|
||||
.buswidth = 4,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_EBI1_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_0 = {
|
||||
.name = "qnm_camnoc_hf_cam_ife_0",
|
||||
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_0,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_0 = {
|
||||
.name = "qnm_camnoc_icp_cam_ife_0",
|
||||
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_0 = {
|
||||
.name = "qnm_camnoc_sf_cam_ife_0",
|
||||
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_0,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_1 = {
|
||||
.name = "qnm_mnoc_hf_cam_ife_1",
|
||||
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_1 = {
|
||||
.name = "qnm_mnoc_sf_cam_ife_1",
|
||||
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_pcie_cam_ife_1 = {
|
||||
.name = "qnm_pcie_cam_ife_1",
|
||||
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1,
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node llcc_mc_cam_ife_1 = {
|
||||
.name = "llcc_mc_cam_ife_1",
|
||||
.id = SM8550_MASTER_LLCC_CAM_IFE_1,
|
||||
.channels = 4,
|
||||
.buswidth = 4,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_EBI1_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_1 = {
|
||||
.name = "qnm_camnoc_hf_cam_ife_1",
|
||||
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_1,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_1 = {
|
||||
.name = "qnm_camnoc_icp_cam_ife_1",
|
||||
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_1 = {
|
||||
.name = "qnm_camnoc_sf_cam_ife_1",
|
||||
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_1,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_2 = {
|
||||
.name = "qnm_mnoc_hf_cam_ife_2",
|
||||
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_2 = {
|
||||
.name = "qnm_mnoc_sf_cam_ife_2",
|
||||
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_pcie_cam_ife_2 = {
|
||||
.name = "qnm_pcie_cam_ife_2",
|
||||
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2,
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node llcc_mc_cam_ife_2 = {
|
||||
.name = "llcc_mc_cam_ife_2",
|
||||
.id = SM8550_MASTER_LLCC_CAM_IFE_2,
|
||||
.channels = 4,
|
||||
.buswidth = 4,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_EBI1_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_2 = {
|
||||
.name = "qnm_camnoc_hf_cam_ife_2",
|
||||
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_2,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_2 = {
|
||||
.name = "qnm_camnoc_icp_cam_ife_2",
|
||||
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_2 = {
|
||||
.name = "qnm_camnoc_sf_cam_ife_2",
|
||||
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_2,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_a1noc_snoc = {
|
||||
.name = "qns_a1noc_snoc",
|
||||
.id = SM8550_SLAVE_A1NOC_SNOC,
|
||||
@ -1342,137 +1117,6 @@ static struct qcom_icc_node qns_gemnoc_sf = {
|
||||
.links = { SM8550_MASTER_SNOC_SF_MEM_NOC },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_llcc_disp = {
|
||||
.name = "qns_llcc_disp",
|
||||
.id = SM8550_SLAVE_LLCC_DISP,
|
||||
.channels = 4,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_LLCC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node ebi_disp = {
|
||||
.name = "ebi_disp",
|
||||
.id = SM8550_SLAVE_EBI1_DISP,
|
||||
.channels = 4,
|
||||
.buswidth = 4,
|
||||
.num_links = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_mem_noc_hf_disp = {
|
||||
.name = "qns_mem_noc_hf_disp",
|
||||
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_llcc_cam_ife_0 = {
|
||||
.name = "qns_llcc_cam_ife_0",
|
||||
.id = SM8550_SLAVE_LLCC_CAM_IFE_0,
|
||||
.channels = 4,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_LLCC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node ebi_cam_ife_0 = {
|
||||
.name = "ebi_cam_ife_0",
|
||||
.id = SM8550_SLAVE_EBI1_CAM_IFE_0,
|
||||
.channels = 4,
|
||||
.buswidth = 4,
|
||||
.num_links = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_0 = {
|
||||
.name = "qns_mem_noc_hf_cam_ife_0",
|
||||
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_0 = {
|
||||
.name = "qns_mem_noc_sf_cam_ife_0",
|
||||
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_llcc_cam_ife_1 = {
|
||||
.name = "qns_llcc_cam_ife_1",
|
||||
.id = SM8550_SLAVE_LLCC_CAM_IFE_1,
|
||||
.channels = 4,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_LLCC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node ebi_cam_ife_1 = {
|
||||
.name = "ebi_cam_ife_1",
|
||||
.id = SM8550_SLAVE_EBI1_CAM_IFE_1,
|
||||
.channels = 4,
|
||||
.buswidth = 4,
|
||||
.num_links = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_1 = {
|
||||
.name = "qns_mem_noc_hf_cam_ife_1",
|
||||
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_1 = {
|
||||
.name = "qns_mem_noc_sf_cam_ife_1",
|
||||
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_llcc_cam_ife_2 = {
|
||||
.name = "qns_llcc_cam_ife_2",
|
||||
.id = SM8550_SLAVE_LLCC_CAM_IFE_2,
|
||||
.channels = 4,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_LLCC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node ebi_cam_ife_2 = {
|
||||
.name = "ebi_cam_ife_2",
|
||||
.id = SM8550_SLAVE_EBI1_CAM_IFE_2,
|
||||
.channels = 4,
|
||||
.buswidth = 4,
|
||||
.num_links = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_2 = {
|
||||
.name = "qns_mem_noc_hf_cam_ife_2",
|
||||
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
|
||||
.name = "qns_mem_noc_sf_cam_ife_2",
|
||||
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x8,
|
||||
@ -1639,161 +1283,6 @@ static struct qcom_icc_bcm bcm_sn7 = {
|
||||
.nodes = { &qns_pcie_mem_noc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv_disp = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mc0_disp = {
|
||||
.name = "MC0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm0_disp = {
|
||||
.name = "MM0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_mem_noc_hf_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh0_disp = {
|
||||
.name = "SH0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_llcc_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh1_disp = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 2,
|
||||
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x0,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = {
|
||||
.name = "MC0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
|
||||
.name = "MM0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_mem_noc_hf_cam_ife_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 4,
|
||||
.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
|
||||
&qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
|
||||
.name = "SH0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_llcc_cam_ife_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
|
||||
&qnm_pcie_cam_ife_0 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x0,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = {
|
||||
.name = "MC0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
|
||||
.name = "MM0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_mem_noc_hf_cam_ife_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 4,
|
||||
.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
|
||||
&qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
|
||||
.name = "SH0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_llcc_cam_ife_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
|
||||
&qnm_pcie_cam_ife_1 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x0,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = {
|
||||
.name = "MC0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
|
||||
.name = "MM0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_mem_noc_hf_cam_ife_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 4,
|
||||
.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
|
||||
&qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
|
||||
.name = "SH0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_llcc_cam_ife_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
|
||||
&qnm_pcie_cam_ife_2 },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
|
||||
};
|
||||
|
||||
@ -1945,14 +1434,6 @@ static const struct qcom_icc_desc sm8550_cnoc_main = {
|
||||
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
|
||||
&bcm_sh0,
|
||||
&bcm_sh1,
|
||||
&bcm_sh0_disp,
|
||||
&bcm_sh1_disp,
|
||||
&bcm_sh0_cam_ife_0,
|
||||
&bcm_sh1_cam_ife_0,
|
||||
&bcm_sh0_cam_ife_1,
|
||||
&bcm_sh1_cam_ife_1,
|
||||
&bcm_sh0_cam_ife_2,
|
||||
&bcm_sh1_cam_ife_2,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const gem_noc_nodes[] = {
|
||||
@ -1971,21 +1452,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
|
||||
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
|
||||
[SLAVE_LLCC] = &qns_llcc,
|
||||
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
|
||||
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
|
||||
[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
|
||||
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
|
||||
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_hf_cam_ife_0,
|
||||
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_sf_cam_ife_0,
|
||||
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0] = &qnm_pcie_cam_ife_0,
|
||||
[SLAVE_LLCC_CAM_IFE_0] = &qns_llcc_cam_ife_0,
|
||||
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_hf_cam_ife_1,
|
||||
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_sf_cam_ife_1,
|
||||
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1] = &qnm_pcie_cam_ife_1,
|
||||
[SLAVE_LLCC_CAM_IFE_1] = &qns_llcc_cam_ife_1,
|
||||
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_hf_cam_ife_2,
|
||||
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_sf_cam_ife_2,
|
||||
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2] = &qnm_pcie_cam_ife_2,
|
||||
[SLAVE_LLCC_CAM_IFE_2] = &qns_llcc_cam_ife_2,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm8550_gem_noc = {
|
||||
@ -2044,27 +1510,11 @@ static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
|
||||
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
|
||||
&bcm_acv,
|
||||
&bcm_mc0,
|
||||
&bcm_acv_disp,
|
||||
&bcm_mc0_disp,
|
||||
&bcm_acv_cam_ife_0,
|
||||
&bcm_mc0_cam_ife_0,
|
||||
&bcm_acv_cam_ife_1,
|
||||
&bcm_mc0_cam_ife_1,
|
||||
&bcm_acv_cam_ife_2,
|
||||
&bcm_mc0_cam_ife_2,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const mc_virt_nodes[] = {
|
||||
[MASTER_LLCC] = &llcc_mc,
|
||||
[SLAVE_EBI1] = &ebi,
|
||||
[MASTER_LLCC_DISP] = &llcc_mc_disp,
|
||||
[SLAVE_EBI1_DISP] = &ebi_disp,
|
||||
[MASTER_LLCC_CAM_IFE_0] = &llcc_mc_cam_ife_0,
|
||||
[SLAVE_EBI1_CAM_IFE_0] = &ebi_cam_ife_0,
|
||||
[MASTER_LLCC_CAM_IFE_1] = &llcc_mc_cam_ife_1,
|
||||
[SLAVE_EBI1_CAM_IFE_1] = &ebi_cam_ife_1,
|
||||
[MASTER_LLCC_CAM_IFE_2] = &llcc_mc_cam_ife_2,
|
||||
[SLAVE_EBI1_CAM_IFE_2] = &ebi_cam_ife_2,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm8550_mc_virt = {
|
||||
@ -2077,13 +1527,6 @@ static const struct qcom_icc_desc sm8550_mc_virt = {
|
||||
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
|
||||
&bcm_mm0,
|
||||
&bcm_mm1,
|
||||
&bcm_mm0_disp,
|
||||
&bcm_mm0_cam_ife_0,
|
||||
&bcm_mm1_cam_ife_0,
|
||||
&bcm_mm0_cam_ife_1,
|
||||
&bcm_mm1_cam_ife_1,
|
||||
&bcm_mm0_cam_ife_2,
|
||||
&bcm_mm1_cam_ife_2,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const mmss_noc_nodes[] = {
|
||||
@ -2100,23 +1543,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
|
||||
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
|
||||
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
|
||||
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
|
||||
[MASTER_MDP_DISP] = &qnm_mdp_disp,
|
||||
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
|
||||
[MASTER_CAMNOC_HF_CAM_IFE_0] = &qnm_camnoc_hf_cam_ife_0,
|
||||
[MASTER_CAMNOC_ICP_CAM_IFE_0] = &qnm_camnoc_icp_cam_ife_0,
|
||||
[MASTER_CAMNOC_SF_CAM_IFE_0] = &qnm_camnoc_sf_cam_ife_0,
|
||||
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_hf_cam_ife_0,
|
||||
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_sf_cam_ife_0,
|
||||
[MASTER_CAMNOC_HF_CAM_IFE_1] = &qnm_camnoc_hf_cam_ife_1,
|
||||
[MASTER_CAMNOC_ICP_CAM_IFE_1] = &qnm_camnoc_icp_cam_ife_1,
|
||||
[MASTER_CAMNOC_SF_CAM_IFE_1] = &qnm_camnoc_sf_cam_ife_1,
|
||||
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_hf_cam_ife_1,
|
||||
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_sf_cam_ife_1,
|
||||
[MASTER_CAMNOC_HF_CAM_IFE_2] = &qnm_camnoc_hf_cam_ife_2,
|
||||
[MASTER_CAMNOC_ICP_CAM_IFE_2] = &qnm_camnoc_icp_cam_ife_2,
|
||||
[MASTER_CAMNOC_SF_CAM_IFE_2] = &qnm_camnoc_sf_cam_ife_2,
|
||||
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_hf_cam_ife_2,
|
||||
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_sf_cam_ife_2,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sm8550_mmss_noc = {
|
||||
|
||||
@ -12,167 +12,127 @@
|
||||
#define SM8550_MASTER_A1NOC_SNOC 0
|
||||
#define SM8550_MASTER_A2NOC_SNOC 1
|
||||
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2
|
||||
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 3
|
||||
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 4
|
||||
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 5
|
||||
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP 6
|
||||
#define SM8550_MASTER_APPSS_PROC 7
|
||||
#define SM8550_MASTER_CAMNOC_HF 8
|
||||
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_0 9
|
||||
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_1 10
|
||||
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_2 11
|
||||
#define SM8550_MASTER_CAMNOC_ICP 12
|
||||
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0 13
|
||||
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1 14
|
||||
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2 15
|
||||
#define SM8550_MASTER_CAMNOC_SF 16
|
||||
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_0 17
|
||||
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_1 18
|
||||
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_2 19
|
||||
#define SM8550_MASTER_CDSP_HCP 20
|
||||
#define SM8550_MASTER_CDSP_PROC 21
|
||||
#define SM8550_MASTER_CNOC_CFG 22
|
||||
#define SM8550_MASTER_CNOC_MNOC_CFG 23
|
||||
#define SM8550_MASTER_COMPUTE_NOC 24
|
||||
#define SM8550_MASTER_CRYPTO 25
|
||||
#define SM8550_MASTER_GEM_NOC_CNOC 26
|
||||
#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 27
|
||||
#define SM8550_MASTER_GFX3D 28
|
||||
#define SM8550_MASTER_GIC 29
|
||||
#define SM8550_MASTER_GIC_AHB 30
|
||||
#define SM8550_MASTER_GPU_TCU 31
|
||||
#define SM8550_MASTER_IPA 32
|
||||
#define SM8550_MASTER_LLCC 33
|
||||
#define SM8550_MASTER_LLCC_CAM_IFE_0 34
|
||||
#define SM8550_MASTER_LLCC_CAM_IFE_1 35
|
||||
#define SM8550_MASTER_LLCC_CAM_IFE_2 36
|
||||
#define SM8550_MASTER_LLCC_DISP 37
|
||||
#define SM8550_MASTER_LPASS_GEM_NOC 38
|
||||
#define SM8550_MASTER_LPASS_LPINOC 39
|
||||
#define SM8550_MASTER_LPASS_PROC 40
|
||||
#define SM8550_MASTER_LPIAON_NOC 41
|
||||
#define SM8550_MASTER_MDP 42
|
||||
#define SM8550_MASTER_MDP_DISP 43
|
||||
#define SM8550_MASTER_MNOC_HF_MEM_NOC 44
|
||||
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 45
|
||||
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 46
|
||||
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 47
|
||||
#define SM8550_MASTER_MNOC_HF_MEM_NOC_DISP 48
|
||||
#define SM8550_MASTER_MNOC_SF_MEM_NOC 49
|
||||
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 50
|
||||
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 51
|
||||
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 52
|
||||
#define SM8550_MASTER_MSS_PROC 53
|
||||
#define SM8550_MASTER_PCIE_0 54
|
||||
#define SM8550_MASTER_PCIE_1 55
|
||||
#define SM8550_MASTER_PCIE_ANOC_CFG 56
|
||||
#define SM8550_MASTER_QDSS_BAM 57
|
||||
#define SM8550_MASTER_QDSS_ETR 58
|
||||
#define SM8550_MASTER_QDSS_ETR_1 59
|
||||
#define SM8550_MASTER_QSPI_0 60
|
||||
#define SM8550_MASTER_QUP_1 61
|
||||
#define SM8550_MASTER_QUP_2 62
|
||||
#define SM8550_MASTER_QUP_CORE_0 63
|
||||
#define SM8550_MASTER_QUP_CORE_1 64
|
||||
#define SM8550_MASTER_QUP_CORE_2 65
|
||||
#define SM8550_MASTER_SDCC_2 66
|
||||
#define SM8550_MASTER_SDCC_4 67
|
||||
#define SM8550_MASTER_SNOC_GC_MEM_NOC 68
|
||||
#define SM8550_MASTER_SNOC_SF_MEM_NOC 69
|
||||
#define SM8550_MASTER_SP 70
|
||||
#define SM8550_MASTER_SYS_TCU 71
|
||||
#define SM8550_MASTER_UFS_MEM 72
|
||||
#define SM8550_MASTER_USB3_0 73
|
||||
#define SM8550_MASTER_VIDEO 74
|
||||
#define SM8550_MASTER_VIDEO_CV_PROC 75
|
||||
#define SM8550_MASTER_VIDEO_PROC 76
|
||||
#define SM8550_MASTER_VIDEO_V_PROC 77
|
||||
#define SM8550_SLAVE_A1NOC_SNOC 78
|
||||
#define SM8550_SLAVE_A2NOC_SNOC 79
|
||||
#define SM8550_SLAVE_AHB2PHY_NORTH 80
|
||||
#define SM8550_SLAVE_AHB2PHY_SOUTH 81
|
||||
#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 82
|
||||
#define SM8550_SLAVE_AOSS 83
|
||||
#define SM8550_SLAVE_APPSS 84
|
||||
#define SM8550_SLAVE_BOOT_IMEM 85
|
||||
#define SM8550_SLAVE_CAMERA_CFG 86
|
||||
#define SM8550_SLAVE_CDSP_MEM_NOC 87
|
||||
#define SM8550_SLAVE_CLK_CTL 88
|
||||
#define SM8550_SLAVE_CNOC_CFG 89
|
||||
#define SM8550_SLAVE_CNOC_MNOC_CFG 90
|
||||
#define SM8550_SLAVE_CNOC_MSS 91
|
||||
#define SM8550_SLAVE_CPR_NSPCX 92
|
||||
#define SM8550_SLAVE_CRYPTO_0_CFG 93
|
||||
#define SM8550_SLAVE_CX_RDPM 94
|
||||
#define SM8550_SLAVE_DDRSS_CFG 95
|
||||
#define SM8550_SLAVE_DISPLAY_CFG 96
|
||||
#define SM8550_SLAVE_EBI1 97
|
||||
#define SM8550_SLAVE_EBI1_CAM_IFE_0 98
|
||||
#define SM8550_SLAVE_EBI1_CAM_IFE_1 99
|
||||
#define SM8550_SLAVE_EBI1_CAM_IFE_2 100
|
||||
#define SM8550_SLAVE_EBI1_DISP 101
|
||||
#define SM8550_SLAVE_GEM_NOC_CNOC 102
|
||||
#define SM8550_SLAVE_GFX3D_CFG 103
|
||||
#define SM8550_SLAVE_I2C 104
|
||||
#define SM8550_SLAVE_IMEM 105
|
||||
#define SM8550_SLAVE_IMEM_CFG 106
|
||||
#define SM8550_SLAVE_IPA_CFG 107
|
||||
#define SM8550_SLAVE_IPC_ROUTER_CFG 108
|
||||
#define SM8550_SLAVE_LLCC 109
|
||||
#define SM8550_SLAVE_LLCC_CAM_IFE_0 110
|
||||
#define SM8550_SLAVE_LLCC_CAM_IFE_1 111
|
||||
#define SM8550_SLAVE_LLCC_CAM_IFE_2 112
|
||||
#define SM8550_SLAVE_LLCC_DISP 113
|
||||
#define SM8550_SLAVE_LPASS_GEM_NOC 114
|
||||
#define SM8550_SLAVE_LPASS_QTB_CFG 115
|
||||
#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 116
|
||||
#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 117
|
||||
#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 118
|
||||
#define SM8550_SLAVE_MNOC_HF_MEM_NOC 119
|
||||
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 120
|
||||
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 121
|
||||
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 122
|
||||
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP 123
|
||||
#define SM8550_SLAVE_MNOC_SF_MEM_NOC 124
|
||||
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 125
|
||||
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 126
|
||||
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 127
|
||||
#define SM8550_SLAVE_MX_RDPM 128
|
||||
#define SM8550_SLAVE_NSP_QTB_CFG 129
|
||||
#define SM8550_SLAVE_PCIE_0 130
|
||||
#define SM8550_SLAVE_PCIE_0_CFG 131
|
||||
#define SM8550_SLAVE_PCIE_1 132
|
||||
#define SM8550_SLAVE_PCIE_1_CFG 133
|
||||
#define SM8550_SLAVE_PCIE_ANOC_CFG 134
|
||||
#define SM8550_SLAVE_PDM 135
|
||||
#define SM8550_SLAVE_PIMEM_CFG 136
|
||||
#define SM8550_SLAVE_PRNG 137
|
||||
#define SM8550_SLAVE_QDSS_CFG 138
|
||||
#define SM8550_SLAVE_QDSS_STM 139
|
||||
#define SM8550_SLAVE_QSPI_0 140
|
||||
#define SM8550_SLAVE_QUP_1 141
|
||||
#define SM8550_SLAVE_QUP_2 142
|
||||
#define SM8550_SLAVE_QUP_CORE_0 143
|
||||
#define SM8550_SLAVE_QUP_CORE_1 144
|
||||
#define SM8550_SLAVE_QUP_CORE_2 145
|
||||
#define SM8550_SLAVE_RBCPR_CX_CFG 146
|
||||
#define SM8550_SLAVE_RBCPR_MMCX_CFG 147
|
||||
#define SM8550_SLAVE_RBCPR_MXA_CFG 148
|
||||
#define SM8550_SLAVE_RBCPR_MXC_CFG 149
|
||||
#define SM8550_SLAVE_SDCC_2 150
|
||||
#define SM8550_SLAVE_SDCC_4 151
|
||||
#define SM8550_SLAVE_SERVICE_MNOC 152
|
||||
#define SM8550_SLAVE_SERVICE_PCIE_ANOC 153
|
||||
#define SM8550_SLAVE_SNOC_GEM_NOC_GC 154
|
||||
#define SM8550_SLAVE_SNOC_GEM_NOC_SF 155
|
||||
#define SM8550_SLAVE_SPSS_CFG 156
|
||||
#define SM8550_SLAVE_TCSR 157
|
||||
#define SM8550_SLAVE_TCU 158
|
||||
#define SM8550_SLAVE_TLMM 159
|
||||
#define SM8550_SLAVE_TME_CFG 160
|
||||
#define SM8550_SLAVE_UFS_MEM_CFG 161
|
||||
#define SM8550_SLAVE_USB3_0 162
|
||||
#define SM8550_SLAVE_VENUS_CFG 163
|
||||
#define SM8550_SLAVE_VSENSE_CTRL_CFG 164
|
||||
#define SM8550_MASTER_APPSS_PROC 3
|
||||
#define SM8550_MASTER_CAMNOC_HF 4
|
||||
#define SM8550_MASTER_CAMNOC_ICP 5
|
||||
#define SM8550_MASTER_CAMNOC_SF 6
|
||||
#define SM8550_MASTER_CDSP_HCP 7
|
||||
#define SM8550_MASTER_CDSP_PROC 8
|
||||
#define SM8550_MASTER_CNOC_CFG 9
|
||||
#define SM8550_MASTER_CNOC_MNOC_CFG 10
|
||||
#define SM8550_MASTER_COMPUTE_NOC 11
|
||||
#define SM8550_MASTER_CRYPTO 12
|
||||
#define SM8550_MASTER_GEM_NOC_CNOC 13
|
||||
#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14
|
||||
#define SM8550_MASTER_GFX3D 15
|
||||
#define SM8550_MASTER_GIC 16
|
||||
#define SM8550_MASTER_GIC_AHB 17
|
||||
#define SM8550_MASTER_GPU_TCU 18
|
||||
#define SM8550_MASTER_IPA 19
|
||||
#define SM8550_MASTER_LLCC 20
|
||||
#define SM8550_MASTER_LPASS_GEM_NOC 21
|
||||
#define SM8550_MASTER_LPASS_LPINOC 22
|
||||
#define SM8550_MASTER_LPASS_PROC 23
|
||||
#define SM8550_MASTER_LPIAON_NOC 24
|
||||
#define SM8550_MASTER_MDP 25
|
||||
#define SM8550_MASTER_MNOC_HF_MEM_NOC 26
|
||||
#define SM8550_MASTER_MNOC_SF_MEM_NOC 27
|
||||
#define SM8550_MASTER_MSS_PROC 28
|
||||
#define SM8550_MASTER_PCIE_0 29
|
||||
#define SM8550_MASTER_PCIE_1 30
|
||||
#define SM8550_MASTER_PCIE_ANOC_CFG 31
|
||||
#define SM8550_MASTER_QDSS_BAM 32
|
||||
#define SM8550_MASTER_QDSS_ETR 33
|
||||
#define SM8550_MASTER_QDSS_ETR_1 34
|
||||
#define SM8550_MASTER_QSPI_0 35
|
||||
#define SM8550_MASTER_QUP_1 36
|
||||
#define SM8550_MASTER_QUP_2 37
|
||||
#define SM8550_MASTER_QUP_CORE_0 38
|
||||
#define SM8550_MASTER_QUP_CORE_1 39
|
||||
#define SM8550_MASTER_QUP_CORE_2 40
|
||||
#define SM8550_MASTER_SDCC_2 41
|
||||
#define SM8550_MASTER_SDCC_4 42
|
||||
#define SM8550_MASTER_SNOC_GC_MEM_NOC 43
|
||||
#define SM8550_MASTER_SNOC_SF_MEM_NOC 44
|
||||
#define SM8550_MASTER_SP 45
|
||||
#define SM8550_MASTER_SYS_TCU 46
|
||||
#define SM8550_MASTER_UFS_MEM 47
|
||||
#define SM8550_MASTER_USB3_0 48
|
||||
#define SM8550_MASTER_VIDEO 49
|
||||
#define SM8550_MASTER_VIDEO_CV_PROC 50
|
||||
#define SM8550_MASTER_VIDEO_PROC 51
|
||||
#define SM8550_MASTER_VIDEO_V_PROC 52
|
||||
#define SM8550_SLAVE_A1NOC_SNOC 53
|
||||
#define SM8550_SLAVE_A2NOC_SNOC 54
|
||||
#define SM8550_SLAVE_AHB2PHY_NORTH 55
|
||||
#define SM8550_SLAVE_AHB2PHY_SOUTH 56
|
||||
#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57
|
||||
#define SM8550_SLAVE_AOSS 58
|
||||
#define SM8550_SLAVE_APPSS 59
|
||||
#define SM8550_SLAVE_BOOT_IMEM 60
|
||||
#define SM8550_SLAVE_CAMERA_CFG 61
|
||||
#define SM8550_SLAVE_CDSP_MEM_NOC 62
|
||||
#define SM8550_SLAVE_CLK_CTL 63
|
||||
#define SM8550_SLAVE_CNOC_CFG 64
|
||||
#define SM8550_SLAVE_CNOC_MNOC_CFG 65
|
||||
#define SM8550_SLAVE_CNOC_MSS 66
|
||||
#define SM8550_SLAVE_CPR_NSPCX 67
|
||||
#define SM8550_SLAVE_CRYPTO_0_CFG 68
|
||||
#define SM8550_SLAVE_CX_RDPM 69
|
||||
#define SM8550_SLAVE_DDRSS_CFG 70
|
||||
#define SM8550_SLAVE_DISPLAY_CFG 71
|
||||
#define SM8550_SLAVE_EBI1 72
|
||||
#define SM8550_SLAVE_GEM_NOC_CNOC 73
|
||||
#define SM8550_SLAVE_GFX3D_CFG 74
|
||||
#define SM8550_SLAVE_I2C 75
|
||||
#define SM8550_SLAVE_IMEM 76
|
||||
#define SM8550_SLAVE_IMEM_CFG 77
|
||||
#define SM8550_SLAVE_IPA_CFG 78
|
||||
#define SM8550_SLAVE_IPC_ROUTER_CFG 79
|
||||
#define SM8550_SLAVE_LLCC 80
|
||||
#define SM8550_SLAVE_LPASS_GEM_NOC 81
|
||||
#define SM8550_SLAVE_LPASS_QTB_CFG 82
|
||||
#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83
|
||||
#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84
|
||||
#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85
|
||||
#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86
|
||||
#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87
|
||||
#define SM8550_SLAVE_MX_RDPM 88
|
||||
#define SM8550_SLAVE_NSP_QTB_CFG 89
|
||||
#define SM8550_SLAVE_PCIE_0 90
|
||||
#define SM8550_SLAVE_PCIE_0_CFG 91
|
||||
#define SM8550_SLAVE_PCIE_1 92
|
||||
#define SM8550_SLAVE_PCIE_1_CFG 93
|
||||
#define SM8550_SLAVE_PCIE_ANOC_CFG 94
|
||||
#define SM8550_SLAVE_PDM 95
|
||||
#define SM8550_SLAVE_PIMEM_CFG 96
|
||||
#define SM8550_SLAVE_PRNG 97
|
||||
#define SM8550_SLAVE_QDSS_CFG 98
|
||||
#define SM8550_SLAVE_QDSS_STM 99
|
||||
#define SM8550_SLAVE_QSPI_0 100
|
||||
#define SM8550_SLAVE_QUP_1 101
|
||||
#define SM8550_SLAVE_QUP_2 102
|
||||
#define SM8550_SLAVE_QUP_CORE_0 103
|
||||
#define SM8550_SLAVE_QUP_CORE_1 104
|
||||
#define SM8550_SLAVE_QUP_CORE_2 105
|
||||
#define SM8550_SLAVE_RBCPR_CX_CFG 106
|
||||
#define SM8550_SLAVE_RBCPR_MMCX_CFG 107
|
||||
#define SM8550_SLAVE_RBCPR_MXA_CFG 108
|
||||
#define SM8550_SLAVE_RBCPR_MXC_CFG 109
|
||||
#define SM8550_SLAVE_SDCC_2 110
|
||||
#define SM8550_SLAVE_SDCC_4 111
|
||||
#define SM8550_SLAVE_SERVICE_MNOC 112
|
||||
#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113
|
||||
#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114
|
||||
#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115
|
||||
#define SM8550_SLAVE_SPSS_CFG 116
|
||||
#define SM8550_SLAVE_TCSR 117
|
||||
#define SM8550_SLAVE_TCU 118
|
||||
#define SM8550_SLAVE_TLMM 119
|
||||
#define SM8550_SLAVE_TME_CFG 120
|
||||
#define SM8550_SLAVE_UFS_MEM_CFG 121
|
||||
#define SM8550_SLAVE_USB3_0 122
|
||||
#define SM8550_SLAVE_VENUS_CFG 123
|
||||
#define SM8550_SLAVE_VSENSE_CTRL_CFG 124
|
||||
|
||||
#endif
|
||||
|
||||
@ -670,150 +670,6 @@ static struct qcom_icc_node xm_usb4_2 = {
|
||||
.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mnoc_hf_disp = {
|
||||
.name = "qnm_mnoc_hf_disp",
|
||||
.id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_LLCC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_pcie_disp = {
|
||||
.name = "qnm_pcie_disp",
|
||||
.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP,
|
||||
.channels = 1,
|
||||
.buswidth = 64,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_LLCC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node llcc_mc_disp = {
|
||||
.name = "llcc_mc_disp",
|
||||
.id = X1E80100_MASTER_LLCC_DISP,
|
||||
.channels = 8,
|
||||
.buswidth = 4,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_EBI1_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_mdp_disp = {
|
||||
.name = "qnm_mdp_disp",
|
||||
.id = X1E80100_MASTER_MDP_DISP,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_pcie_pcie = {
|
||||
.name = "qnm_pcie_pcie",
|
||||
.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 64,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_LLCC_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node llcc_mc_pcie = {
|
||||
.name = "llcc_mc_pcie",
|
||||
.id = X1E80100_MASTER_LLCC_PCIE,
|
||||
.channels = 8,
|
||||
.buswidth = 4,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_EBI1_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = {
|
||||
.name = "qnm_pcie_north_gem_noc_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_NORTH_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 64,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = {
|
||||
.name = "qnm_pcie_south_gem_noc_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_SOUTH_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 64,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_pcie_3_pcie = {
|
||||
.name = "xm_pcie_3_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_3_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 64,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_pcie_4_pcie = {
|
||||
.name = "xm_pcie_4_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_4_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_pcie_5_pcie = {
|
||||
.name = "xm_pcie_5_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_5_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 8,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_pcie_0_pcie = {
|
||||
.name = "xm_pcie_0_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_0_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_pcie_1_pcie = {
|
||||
.name = "xm_pcie_1_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_1_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_pcie_2_pcie = {
|
||||
.name = "xm_pcie_2_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_2_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_pcie_6a_pcie = {
|
||||
.name = "xm_pcie_6a_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_6A_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node xm_pcie_6b_pcie = {
|
||||
.name = "xm_pcie_6b_pcie",
|
||||
.id = X1E80100_MASTER_PCIE_6B_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_a1noc_snoc = {
|
||||
.name = "qns_a1noc_snoc",
|
||||
.id = X1E80100_SLAVE_A1NOC_SNOC,
|
||||
@ -1514,76 +1370,6 @@ static struct qcom_icc_node qns_aggre_usb_south_snoc = {
|
||||
.links = { X1E80100_MASTER_AGGRE_USB_SOUTH },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_llcc_disp = {
|
||||
.name = "qns_llcc_disp",
|
||||
.id = X1E80100_SLAVE_LLCC_DISP,
|
||||
.channels = 8,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_MASTER_LLCC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node ebi_disp = {
|
||||
.name = "ebi_disp",
|
||||
.id = X1E80100_SLAVE_EBI1_DISP,
|
||||
.channels = 8,
|
||||
.buswidth = 4,
|
||||
.num_links = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_mem_noc_hf_disp = {
|
||||
.name = "qns_mem_noc_hf_disp",
|
||||
.id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP,
|
||||
.channels = 2,
|
||||
.buswidth = 32,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_llcc_pcie = {
|
||||
.name = "qns_llcc_pcie",
|
||||
.id = X1E80100_SLAVE_LLCC_PCIE,
|
||||
.channels = 8,
|
||||
.buswidth = 16,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_MASTER_LLCC_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node ebi_pcie = {
|
||||
.name = "ebi_pcie",
|
||||
.id = X1E80100_SLAVE_EBI1_PCIE,
|
||||
.channels = 8,
|
||||
.buswidth = 4,
|
||||
.num_links = 0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_pcie_mem_noc_pcie = {
|
||||
.name = "qns_pcie_mem_noc_pcie",
|
||||
.id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 64,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = {
|
||||
.name = "qns_pcie_north_gem_noc_pcie",
|
||||
.id = X1E80100_SLAVE_PCIE_NORTH_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 64,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_MASTER_PCIE_NORTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = {
|
||||
.name = "qns_pcie_south_gem_noc_pcie",
|
||||
.id = X1E80100_SLAVE_PCIE_SOUTH_PCIE,
|
||||
.channels = 1,
|
||||
.buswidth = 64,
|
||||
.num_links = 1,
|
||||
.links = { X1E80100_MASTER_PCIE_SOUTH_PCIE },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv = {
|
||||
.name = "ACV",
|
||||
.num_nodes = 1,
|
||||
@ -1755,73 +1541,7 @@ static struct qcom_icc_bcm bcm_sn4 = {
|
||||
.nodes = { &qnm_usb_anoc },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv_disp = {
|
||||
.name = "ACV",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mc0_disp = {
|
||||
.name = "MC0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm0_disp = {
|
||||
.name = "MM0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_mem_noc_hf_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mm1_disp = {
|
||||
.name = "MM1",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_mdp_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh0_disp = {
|
||||
.name = "SH0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_llcc_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh1_disp = {
|
||||
.name = "SH1",
|
||||
.num_nodes = 2,
|
||||
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv_pcie = {
|
||||
.name = "ACV",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_pcie },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_mc0_pcie = {
|
||||
.name = "MC0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_pcie },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_pc0_pcie = {
|
||||
.name = "PC0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_pcie_mem_noc_pcie },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh0_pcie = {
|
||||
.name = "SH0",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qns_llcc_pcie },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_sh1_pcie = {
|
||||
.name = "SH1",
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_pcie_pcie },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
|
||||
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
|
||||
@ -1982,10 +1702,6 @@ static const struct qcom_icc_desc x1e80100_cnoc_main = {
|
||||
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
|
||||
&bcm_sh0,
|
||||
&bcm_sh1,
|
||||
&bcm_sh0_disp,
|
||||
&bcm_sh1_disp,
|
||||
&bcm_sh0_pcie,
|
||||
&bcm_sh1_pcie,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const gem_noc_nodes[] = {
|
||||
@ -2004,11 +1720,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
|
||||
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
|
||||
[SLAVE_LLCC] = &qns_llcc,
|
||||
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
|
||||
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
|
||||
[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
|
||||
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
|
||||
[MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &qnm_pcie_pcie,
|
||||
[SLAVE_LLCC_PCIE] = &qns_llcc_pcie,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc x1e80100_gem_noc = {
|
||||
@ -2018,7 +1729,7 @@ static const struct qcom_icc_desc x1e80100_gem_noc = {
|
||||
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
|
||||
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
|
||||
@ -2067,19 +1778,11 @@ static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
|
||||
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
|
||||
&bcm_acv,
|
||||
&bcm_mc0,
|
||||
&bcm_acv_disp,
|
||||
&bcm_mc0_disp,
|
||||
&bcm_acv_pcie,
|
||||
&bcm_mc0_pcie,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const mc_virt_nodes[] = {
|
||||
[MASTER_LLCC] = &llcc_mc,
|
||||
[SLAVE_EBI1] = &ebi,
|
||||
[MASTER_LLCC_DISP] = &llcc_mc_disp,
|
||||
[SLAVE_EBI1_DISP] = &ebi_disp,
|
||||
[MASTER_LLCC_PCIE] = &llcc_mc_pcie,
|
||||
[SLAVE_EBI1_PCIE] = &ebi_pcie,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc x1e80100_mc_virt = {
|
||||
@ -2092,8 +1795,6 @@ static const struct qcom_icc_desc x1e80100_mc_virt = {
|
||||
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
|
||||
&bcm_mm0,
|
||||
&bcm_mm1,
|
||||
&bcm_mm0_disp,
|
||||
&bcm_mm1_disp,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const mmss_noc_nodes[] = {
|
||||
@ -2110,8 +1811,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
|
||||
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
|
||||
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
|
||||
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
|
||||
[MASTER_MDP_DISP] = &qnm_mdp_disp,
|
||||
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc x1e80100_mmss_noc = {
|
||||
@ -2139,16 +1838,12 @@ static const struct qcom_icc_desc x1e80100_nsp_noc = {
|
||||
|
||||
static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {
|
||||
&bcm_pc0,
|
||||
&bcm_pc0_pcie,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
|
||||
[MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc,
|
||||
[MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc,
|
||||
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
|
||||
[MASTER_PCIE_NORTH_PCIE] = &qnm_pcie_north_gem_noc_pcie,
|
||||
[MASTER_PCIE_SOUTH_PCIE] = &qnm_pcie_south_gem_noc_pcie,
|
||||
[SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &qns_pcie_mem_noc_pcie,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
|
||||
@ -2166,10 +1861,6 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
|
||||
[MASTER_PCIE_4] = &xm_pcie_4,
|
||||
[MASTER_PCIE_5] = &xm_pcie_5,
|
||||
[SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
|
||||
[MASTER_PCIE_3_PCIE] = &xm_pcie_3_pcie,
|
||||
[MASTER_PCIE_4_PCIE] = &xm_pcie_4_pcie,
|
||||
[MASTER_PCIE_5_PCIE] = &xm_pcie_5_pcie,
|
||||
[SLAVE_PCIE_NORTH_PCIE] = &qns_pcie_north_gem_noc_pcie,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
|
||||
@ -2179,7 +1870,7 @@ static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
|
||||
.num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *pcie_south_anoc_bcms[] = {
|
||||
static struct qcom_icc_bcm * const pcie_south_anoc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
|
||||
@ -2189,12 +1880,6 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
|
||||
[MASTER_PCIE_6A] = &xm_pcie_6a,
|
||||
[MASTER_PCIE_6B] = &xm_pcie_6b,
|
||||
[SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
|
||||
[MASTER_PCIE_0_PCIE] = &xm_pcie_0_pcie,
|
||||
[MASTER_PCIE_1_PCIE] = &xm_pcie_1_pcie,
|
||||
[MASTER_PCIE_2_PCIE] = &xm_pcie_2_pcie,
|
||||
[MASTER_PCIE_6A_PCIE] = &xm_pcie_6a_pcie,
|
||||
[MASTER_PCIE_6B_PCIE] = &xm_pcie_6b_pcie,
|
||||
[SLAVE_PCIE_SOUTH_PCIE] = &qns_pcie_south_gem_noc_pcie,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
|
||||
@ -2204,7 +1889,7 @@ static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
|
||||
.num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *system_noc_bcms[] = {
|
||||
static struct qcom_icc_bcm * const system_noc_bcms[] = {
|
||||
&bcm_sn0,
|
||||
&bcm_sn2,
|
||||
&bcm_sn3,
|
||||
@ -2242,7 +1927,7 @@ static const struct qcom_icc_desc x1e80100_usb_center_anoc = {
|
||||
.num_bcms = ARRAY_SIZE(usb_center_anoc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *usb_north_anoc_bcms[] = {
|
||||
static struct qcom_icc_bcm * const usb_north_anoc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
|
||||
@ -2258,7 +1943,7 @@ static const struct qcom_icc_desc x1e80100_usb_north_anoc = {
|
||||
.num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *usb_south_anoc_bcms[] = {
|
||||
static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = {
|
||||
};
|
||||
|
||||
static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
|
||||
|
||||
@ -82,7 +82,7 @@ static int exynos_generic_icc_set(struct icc_node *src, struct icc_node *dst)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct icc_node *exynos_generic_icc_xlate(struct of_phandle_args *spec,
|
||||
static struct icc_node *exynos_generic_icc_xlate(const struct of_phandle_args *spec,
|
||||
void *data)
|
||||
{
|
||||
struct exynos_icc_priv *priv = data;
|
||||
|
||||
@ -755,7 +755,7 @@ const char *const tegra_mc_error_names[8] = {
|
||||
[6] = "SMMU translation error",
|
||||
};
|
||||
|
||||
struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data)
|
||||
struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
|
||||
struct icc_node *node;
|
||||
|
||||
@ -1285,7 +1285,7 @@ to_tegra_emc_provider(struct icc_provider *provider)
|
||||
}
|
||||
|
||||
static struct icc_node_data *
|
||||
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
|
||||
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct icc_provider *provider = data;
|
||||
struct icc_node_data *ndata;
|
||||
|
||||
@ -1170,7 +1170,7 @@ static int tegra124_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
}
|
||||
|
||||
static struct icc_node_data *
|
||||
tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
|
||||
tegra124_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
|
||||
const struct tegra_mc_client *client;
|
||||
|
||||
@ -236,7 +236,7 @@ static int tegra_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst)
|
||||
}
|
||||
|
||||
static struct icc_node *
|
||||
tegra_emc_of_icc_xlate(struct of_phandle_args *spec, void *data)
|
||||
tegra_emc_of_icc_xlate(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct icc_provider *provider = data;
|
||||
struct icc_node *node;
|
||||
|
||||
@ -950,7 +950,7 @@ to_tegra_emc_provider(struct icc_provider *provider)
|
||||
}
|
||||
|
||||
static struct icc_node_data *
|
||||
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
|
||||
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct icc_provider *provider = data;
|
||||
struct icc_node_data *ndata;
|
||||
|
||||
@ -390,7 +390,7 @@ static int tegra20_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
}
|
||||
|
||||
static struct icc_node_data *
|
||||
tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
|
||||
tegra20_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
|
||||
unsigned int i, idx = spec->args[0];
|
||||
|
||||
@ -1468,7 +1468,7 @@ to_tegra_emc_provider(struct icc_provider *provider)
|
||||
}
|
||||
|
||||
static struct icc_node_data *
|
||||
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
|
||||
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct icc_provider *provider = data;
|
||||
struct icc_node_data *ndata;
|
||||
|
||||
@ -1332,7 +1332,7 @@ static int tegra30_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
}
|
||||
|
||||
static struct icc_node_data *
|
||||
tegra30_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
|
||||
tegra30_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
|
||||
const struct tegra_mc_client *client;
|
||||
|
||||
@ -112,11 +112,6 @@
|
||||
#define SLAVE_GEM_NOC_CNOC 12
|
||||
#define SLAVE_LLCC 13
|
||||
#define SLAVE_MEM_NOC_PCIE_SNOC 14
|
||||
#define MASTER_MNOC_HF_MEM_NOC_DISP 15
|
||||
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16
|
||||
#define SLAVE_LLCC_DISP 17
|
||||
#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18
|
||||
#define SLAVE_LLCC_PCIE 19
|
||||
|
||||
#define MASTER_LPIAON_NOC 0
|
||||
#define SLAVE_LPASS_GEM_NOC 1
|
||||
@ -129,10 +124,6 @@
|
||||
|
||||
#define MASTER_LLCC 0
|
||||
#define SLAVE_EBI1 1
|
||||
#define MASTER_LLCC_DISP 2
|
||||
#define SLAVE_EBI1_DISP 3
|
||||
#define MASTER_LLCC_PCIE 4
|
||||
#define SLAVE_EBI1_PCIE 5
|
||||
|
||||
#define MASTER_AV1_ENC 0
|
||||
#define MASTER_CAMNOC_HF 1
|
||||
@ -147,8 +138,6 @@
|
||||
#define SLAVE_MNOC_HF_MEM_NOC 10
|
||||
#define SLAVE_MNOC_SF_MEM_NOC 11
|
||||
#define SLAVE_SERVICE_MNOC 12
|
||||
#define MASTER_MDP_DISP 13
|
||||
#define SLAVE_MNOC_HF_MEM_NOC_DISP 14
|
||||
|
||||
#define MASTER_CDSP_PROC 0
|
||||
#define SLAVE_CDSP_MEM_NOC 1
|
||||
@ -156,18 +145,11 @@
|
||||
#define MASTER_PCIE_NORTH 0
|
||||
#define MASTER_PCIE_SOUTH 1
|
||||
#define SLAVE_ANOC_PCIE_GEM_NOC 2
|
||||
#define MASTER_PCIE_NORTH_PCIE 3
|
||||
#define MASTER_PCIE_SOUTH_PCIE 4
|
||||
#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5
|
||||
|
||||
#define MASTER_PCIE_3 0
|
||||
#define MASTER_PCIE_4 1
|
||||
#define MASTER_PCIE_5 2
|
||||
#define SLAVE_PCIE_NORTH 3
|
||||
#define MASTER_PCIE_3_PCIE 4
|
||||
#define MASTER_PCIE_4_PCIE 5
|
||||
#define MASTER_PCIE_5_PCIE 6
|
||||
#define SLAVE_PCIE_NORTH_PCIE 7
|
||||
|
||||
#define MASTER_PCIE_0 0
|
||||
#define MASTER_PCIE_1 1
|
||||
@ -175,12 +157,6 @@
|
||||
#define MASTER_PCIE_6A 3
|
||||
#define MASTER_PCIE_6B 4
|
||||
#define SLAVE_PCIE_SOUTH 5
|
||||
#define MASTER_PCIE_0_PCIE 6
|
||||
#define MASTER_PCIE_1_PCIE 7
|
||||
#define MASTER_PCIE_2_PCIE 8
|
||||
#define MASTER_PCIE_6A_PCIE 9
|
||||
#define MASTER_PCIE_6B_PCIE 10
|
||||
#define SLAVE_PCIE_SOUTH_PCIE 11
|
||||
|
||||
#define MASTER_A1NOC_SNOC 0
|
||||
#define MASTER_A2NOC_SNOC 1
|
||||
|
||||
@ -36,7 +36,7 @@ struct icc_onecell_data {
|
||||
struct icc_node *nodes[] __counted_by(num_nodes);
|
||||
};
|
||||
|
||||
struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
|
||||
struct icc_node *of_icc_xlate_onecell(const struct of_phandle_args *spec,
|
||||
void *data);
|
||||
|
||||
/**
|
||||
@ -65,8 +65,9 @@ struct icc_provider {
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
|
||||
void (*pre_aggregate)(struct icc_node *node);
|
||||
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
|
||||
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
|
||||
struct icc_node_data* (*xlate_extended)(struct of_phandle_args *spec, void *data);
|
||||
struct icc_node* (*xlate)(const struct of_phandle_args *spec, void *data);
|
||||
struct icc_node_data* (*xlate_extended)(const struct of_phandle_args *spec,
|
||||
void *data);
|
||||
struct device *dev;
|
||||
int users;
|
||||
bool inter_set;
|
||||
@ -124,7 +125,7 @@ int icc_nodes_remove(struct icc_provider *provider);
|
||||
void icc_provider_init(struct icc_provider *provider);
|
||||
int icc_provider_register(struct icc_provider *provider);
|
||||
void icc_provider_deregister(struct icc_provider *provider);
|
||||
struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec);
|
||||
struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec);
|
||||
void icc_sync_state(struct device *dev);
|
||||
|
||||
#else
|
||||
@ -171,7 +172,7 @@ static inline int icc_provider_register(struct icc_provider *provider)
|
||||
|
||||
static inline void icc_provider_deregister(struct icc_provider *provider) { }
|
||||
|
||||
static inline struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
|
||||
static inline struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec)
|
||||
{
|
||||
return ERR_PTR(-ENOTSUPP);
|
||||
}
|
||||
|
||||
@ -146,13 +146,14 @@ struct tegra_mc_icc_ops {
|
||||
int (*set)(struct icc_node *src, struct icc_node *dst);
|
||||
int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
|
||||
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
|
||||
struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec,
|
||||
struct icc_node* (*xlate)(const struct of_phandle_args *spec, void *data);
|
||||
struct icc_node_data *(*xlate_extended)(const struct of_phandle_args *spec,
|
||||
void *data);
|
||||
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
|
||||
};
|
||||
|
||||
struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data);
|
||||
struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec,
|
||||
void *data);
|
||||
extern const struct tegra_mc_icc_ops tegra_mc_icc_ops;
|
||||
|
||||
struct tegra_mc_ops {
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user