phy: qcom-qmp-combo: cleanup the driver
Remove the conditionals and options that are not used by any of combo USB+DP PHY devices. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-20-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Vinod Koul
parent
86f5ddddcd
commit
6066bac15b
@ -616,24 +616,12 @@ struct qmp_phy_cfg {
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/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
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const struct qmp_phy_init_tbl *serdes_tbl;
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int serdes_tbl_num;
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const struct qmp_phy_init_tbl *serdes_tbl_sec;
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int serdes_tbl_num_sec;
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const struct qmp_phy_init_tbl *tx_tbl;
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int tx_tbl_num;
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const struct qmp_phy_init_tbl *tx_tbl_sec;
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int tx_tbl_num_sec;
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const struct qmp_phy_init_tbl *rx_tbl;
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int rx_tbl_num;
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const struct qmp_phy_init_tbl *rx_tbl_sec;
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int rx_tbl_num_sec;
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const struct qmp_phy_init_tbl *pcs_tbl;
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int pcs_tbl_num;
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const struct qmp_phy_init_tbl *pcs_tbl_sec;
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int pcs_tbl_num_sec;
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const struct qmp_phy_init_tbl *pcs_misc_tbl;
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int pcs_misc_tbl_num;
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const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
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int pcs_misc_tbl_num_sec;
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/* Init sequence for DP PHY block link rates */
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const struct qmp_phy_init_tbl *serdes_tbl_rbr;
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@ -666,14 +654,9 @@ struct qmp_phy_cfg {
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unsigned int start_ctrl;
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unsigned int pwrdn_ctrl;
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unsigned int mask_com_pcs_ready;
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/* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
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unsigned int phy_status;
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/* true, if PHY has a separate PHY_COM control block */
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bool has_phy_com_ctrl;
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/* true, if PHY has a reset for individual lanes */
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bool has_lane_rst;
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/* true, if PHY needs delay after POWER_DOWN */
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bool has_pwrdn_delay;
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/* power_down delay in usec */
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@ -684,9 +667,6 @@ struct qmp_phy_cfg {
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bool has_phy_dp_com_ctrl;
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/* true, if PHY has secondary tx/rx lanes to be configured */
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bool is_dual_lane_phy;
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/* true, if PCS block has no separate SW_RESET register */
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bool no_pcs_sw_reset;
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};
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struct qmp_phy_combo_cfg {
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@ -1084,18 +1064,13 @@ static void qcom_qmp_phy_combo_configure(void __iomem *base,
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static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
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const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
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int serdes_tbl_num = cfg->serdes_tbl_num;
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int ret;
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qcom_qmp_phy_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
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if (cfg->serdes_tbl_sec)
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qcom_qmp_phy_combo_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
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cfg->serdes_tbl_num_sec);
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if (cfg->type == PHY_TYPE_DP) {
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switch (dp_opts->link_rate) {
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@ -1125,27 +1100,6 @@ static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy)
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}
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}
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if (cfg->has_phy_com_ctrl) {
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void __iomem *status;
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unsigned int mask, val;
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qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
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qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
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SERDES_START | PCS_START);
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status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
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mask = cfg->mask_com_pcs_ready;
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ret = readl_poll_timeout(status, val, (val & mask), 10,
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PHY_INIT_COMPLETE_TIMEOUT);
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if (ret) {
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dev_err(qmp->dev,
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"phy common block init timed-out\n");
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return ret;
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}
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}
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return 0;
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}
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@ -1630,7 +1584,6 @@ static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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void __iomem *pcs = qphy->pcs;
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void __iomem *dp_com = qmp->dp_com;
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int ret, i;
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@ -1693,10 +1646,6 @@ static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy)
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qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
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}
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if (cfg->has_phy_com_ctrl) {
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qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
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SW_PWRDN);
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} else {
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if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
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qphy_setbits(pcs,
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cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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@ -1704,7 +1653,6 @@ static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy)
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else
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qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
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cfg->pwrdn_ctrl);
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}
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mutex_unlock(&qmp->phy_mutex);
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@ -1725,7 +1673,6 @@ static int qcom_qmp_phy_combo_com_exit(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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int i = cfg->num_resets;
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mutex_lock(&qmp->phy_mutex);
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@ -1735,14 +1682,6 @@ static int qcom_qmp_phy_combo_com_exit(struct qmp_phy *qphy)
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}
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reset_control_assert(qmp->ufs_reset);
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if (cfg->has_phy_com_ctrl) {
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qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
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SERDES_START | PCS_START);
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qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
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SW_RESET);
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qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
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SW_PWRDN);
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}
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while (--i >= 0)
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reset_control_assert(qmp->resets[i]);
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@ -1764,33 +1703,6 @@ static int qcom_qmp_phy_combo_init(struct phy *phy)
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int ret;
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dev_vdbg(qmp->dev, "Initializing QMP phy\n");
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if (cfg->no_pcs_sw_reset) {
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/*
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* Get UFS reset, which is delayed until now to avoid a
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* circular dependency where UFS needs its PHY, but the PHY
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* needs this UFS reset.
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*/
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if (!qmp->ufs_reset) {
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qmp->ufs_reset =
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devm_reset_control_get_exclusive(qmp->dev,
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"ufsphy");
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if (IS_ERR(qmp->ufs_reset)) {
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ret = PTR_ERR(qmp->ufs_reset);
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dev_err(qmp->dev,
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"failed to get UFS reset: %d\n",
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ret);
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qmp->ufs_reset = NULL;
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return ret;
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}
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}
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ret = reset_control_assert(qmp->ufs_reset);
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if (ret)
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return ret;
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}
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ret = qcom_qmp_phy_combo_com_init(qphy);
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if (ret)
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return ret;
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@ -1809,43 +1721,26 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy)
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void __iomem *tx = qphy->tx;
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void __iomem *rx = qphy->rx;
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void __iomem *pcs = qphy->pcs;
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void __iomem *pcs_misc = qphy->pcs_misc;
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void __iomem *status;
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unsigned int mask, val, ready;
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int ret;
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qcom_qmp_phy_combo_serdes_init(qphy);
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if (cfg->has_lane_rst) {
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ret = reset_control_deassert(qphy->lane_rst);
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if (ret) {
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dev_err(qmp->dev, "lane%d reset deassert failed\n",
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qphy->index);
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return ret;
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}
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}
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ret = clk_prepare_enable(qphy->pipe_clk);
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if (ret) {
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dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
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goto err_reset_lane;
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return ret;
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}
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/* Tx, Rx, and PCS configurations */
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qcom_qmp_phy_combo_configure_lane(tx, cfg->regs,
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cfg->tx_tbl, cfg->tx_tbl_num, 1);
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if (cfg->tx_tbl_sec)
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qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
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cfg->tx_tbl_num_sec, 1);
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/* Configuration for other LANE for USB-DP combo PHY */
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if (cfg->is_dual_lane_phy) {
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qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs,
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cfg->tx_tbl, cfg->tx_tbl_num, 2);
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if (cfg->tx_tbl_sec)
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qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs,
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cfg->tx_tbl_sec,
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cfg->tx_tbl_num_sec, 2);
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}
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/* Configure special DP tx tunings */
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@ -1854,17 +1749,10 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy)
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qcom_qmp_phy_combo_configure_lane(rx, cfg->regs,
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cfg->rx_tbl, cfg->rx_tbl_num, 1);
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if (cfg->rx_tbl_sec)
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qcom_qmp_phy_combo_configure_lane(rx, cfg->regs,
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cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
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if (cfg->is_dual_lane_phy) {
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qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs,
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cfg->rx_tbl, cfg->rx_tbl_num, 2);
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if (cfg->rx_tbl_sec)
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qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs,
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cfg->rx_tbl_sec,
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cfg->rx_tbl_num_sec, 2);
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}
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/* Configure link rate, swing, etc. */
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@ -1872,27 +1760,17 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy)
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cfg->configure_dp_phy(qphy);
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} else {
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qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
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if (cfg->pcs_tbl_sec)
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qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
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cfg->pcs_tbl_num_sec);
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}
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ret = reset_control_deassert(qmp->ufs_reset);
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if (ret)
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goto err_disable_pipe_clk;
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qcom_qmp_phy_combo_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
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cfg->pcs_misc_tbl_num);
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if (cfg->pcs_misc_tbl_sec)
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qcom_qmp_phy_combo_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
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cfg->pcs_misc_tbl_num_sec);
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if (cfg->has_pwrdn_delay)
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usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
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if (cfg->type != PHY_TYPE_DP) {
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/* Pull PHY out of reset state */
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if (!cfg->no_pcs_sw_reset)
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qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* start SerDes and Phy-Coding-Sublayer */
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qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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@ -1912,9 +1790,6 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy)
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err_disable_pipe_clk:
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clk_disable_unprepare(qphy->pipe_clk);
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err_reset_lane:
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if (cfg->has_lane_rst)
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reset_control_assert(qphy->lane_rst);
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return ret;
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}
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@ -1931,7 +1806,6 @@ static int qcom_qmp_phy_combo_power_off(struct phy *phy)
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writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
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} else {
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/* PHY reset */
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if (!cfg->no_pcs_sw_reset)
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qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* stop SerDes and Phy-Coding-Sublayer */
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@ -1953,10 +1827,6 @@ static int qcom_qmp_phy_combo_power_off(struct phy *phy)
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static int qcom_qmp_phy_combo_exit(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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if (cfg->has_lane_rst)
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reset_control_assert(qphy->lane_rst);
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qcom_qmp_phy_combo_com_exit(qphy);
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@ -2431,11 +2301,6 @@ static const struct phy_ops qcom_qmp_phy_combo_dp_ops = {
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.owner = THIS_MODULE,
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};
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static void qcom_qmp_reset_control_put(void *data)
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{
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reset_control_put(data);
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}
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static
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int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id,
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void __iomem *serdes, const struct qmp_phy_cfg *cfg)
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@ -2521,20 +2386,6 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id
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qphy->pipe_clk = NULL;
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}
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/* Get lane reset, if any */
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if (cfg->has_lane_rst) {
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snprintf(prop_name, sizeof(prop_name), "lane%d", id);
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qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
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if (IS_ERR(qphy->lane_rst)) {
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dev_err(dev, "failed to get lane%d reset\n", id);
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return PTR_ERR(qphy->lane_rst);
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}
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ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
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qphy->lane_rst);
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if (ret)
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return ret;
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}
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if (cfg->type == PHY_TYPE_DP)
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ops = &qcom_qmp_phy_combo_dp_ops;
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else
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