drm/msm/dpu: don't clear IRQ register twice
We already clear the IRQ status register before processing IRQs, so do not clear the register again. Especially do not clear the IRQ status _after_ processing the IRQ as this way we can loose the event. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210617222029.463045-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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@ -120,21 +120,6 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
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#define DPU_IRQ_REG(irq_idx) (irq_idx / 32)
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#define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32))
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static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
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int irq_idx)
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{
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int reg_idx;
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if (!intr)
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return;
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reg_idx = DPU_IRQ_REG(irq_idx);
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DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx));
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/* ensure register writes go through */
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wmb();
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}
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/**
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* dpu_core_irq_callback_handler - dispatch core interrupts
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* @arg: private data of callback handler
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@ -203,8 +188,6 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
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dpu_core_irq_callback_handler(dpu_kms, irq_idx);
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dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
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/*
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* When callback finish, clear the irq_status
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* with the matching mask. Once irq_status
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