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MIPS: Malta: Stop using GIC REG macros

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Stop using the REG macros from gic.h and instead use proper iomem
accessors.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8126/
Patchwork: https://patchwork.linux-mips.org/patch/8227/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker 2014-10-20 12:03:51 -07:00 committed by Ralf Baechle
parent 327b8c89d4
commit 609ead041b
1 changed files with 9 additions and 9 deletions
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18
arch/mips/mti-malta/malta-int.c
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@ -37,7 +37,7 @@
#include <asm/setup.h> #include <asm/setup.h>
#include <asm/rtlx.h> #include <asm/rtlx.h>
static unsigned long _msc01_biu_base; static void __iomem *_msc01_biu_base;
static DEFINE_RAW_SPINLOCK(mips_irq_lock); static DEFINE_RAW_SPINLOCK(mips_irq_lock);
@ -293,12 +293,12 @@ void __init arch_init_irq(void)
gic_present = 1; gic_present = 1;
} else { } else {
if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
_msc01_biu_base = (unsigned long) _msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
ioremap_nocache(MSC01_BIU_REG_BASE,
MSC01_BIU_ADDRSPACE_SZ); MSC01_BIU_ADDRSPACE_SZ);
gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & gic_present =
MSC01_SC_CFG_GICPRES_MSK) >> (__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
MSC01_SC_CFG_GICPRES_SHF; MSC01_SC_CFG_GICPRES_MSK) >>
MSC01_SC_CFG_GICPRES_SHF;
} }
} }
if (gic_present) if (gic_present)
@ -336,9 +336,9 @@ void __init arch_init_irq(void)
MIPS_GIC_IRQ_BASE); MIPS_GIC_IRQ_BASE);
if (!mips_cm_present()) { if (!mips_cm_present()) {
/* Enable the GIC */ /* Enable the GIC */
i = REG(_msc01_biu_base, MSC01_SC_CFG); i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
REG(_msc01_biu_base, MSC01_SC_CFG) = __raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
(i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); _msc01_biu_base + MSC01_SC_CFG_OFS);
pr_debug("GIC Enabled\n"); pr_debug("GIC Enabled\n");
} }
i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A; i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;