drm/amd/display: Create optc.h file
For all the components that participate in DCN architecture, there is a header in the dc/inch/hw. For some reason, OPTC broke this pattern and added all the primary functions/structs associated with that in the dcn10_optc.h file. For consistency's sake, this commit introduces a new optc.h file and extracts the code from dcn10_optc to this new file. Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira
Alex Deucher
parent
3e18d4bd9a
commit
60ccd588d5
@ -37,7 +37,7 @@
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_atomic.h>
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#include "dcn10/dcn10_optc.h"
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#include "dc/inc/hw/optc.h"
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#include "dc/inc/core_types.h"
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@ -26,7 +26,7 @@
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#ifndef __DC_TIMING_GENERATOR_DCN10_H__
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#define __DC_TIMING_GENERATOR_DCN10_H__
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#include "timing_generator.h"
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#include "optc.h"
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#define DCN10TG_FROM_TG(tg)\
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container_of(tg, struct optc, base)
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@ -594,190 +594,6 @@ struct dcn_optc_mask {
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TG_REG_FIELD_LIST_DCN3_5(uint32_t)
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};
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struct optc {
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struct timing_generator base;
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const struct dcn_optc_registers *tg_regs;
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const struct dcn_optc_shift *tg_shift;
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const struct dcn_optc_mask *tg_mask;
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int opp_count;
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uint32_t max_h_total;
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uint32_t max_v_total;
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uint32_t min_h_blank;
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uint32_t min_h_sync_width;
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uint32_t min_v_sync_width;
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uint32_t min_v_blank;
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uint32_t min_v_blank_interlace;
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int vstartup_start;
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int vupdate_offset;
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int vupdate_width;
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int vready_offset;
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struct dc_crtc_timing orginal_patched_timing;
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enum signal_type signal;
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};
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void dcn10_timing_generator_init(struct optc *optc);
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struct dcn_otg_state {
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uint32_t v_blank_start;
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uint32_t v_blank_end;
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uint32_t v_sync_a_pol;
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uint32_t v_total;
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uint32_t v_total_max;
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uint32_t v_total_min;
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uint32_t v_total_min_sel;
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uint32_t v_total_max_sel;
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uint32_t v_sync_a_start;
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uint32_t v_sync_a_end;
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uint32_t h_blank_start;
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uint32_t h_blank_end;
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uint32_t h_sync_a_start;
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uint32_t h_sync_a_end;
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uint32_t h_sync_a_pol;
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uint32_t h_total;
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uint32_t underflow_occurred_status;
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uint32_t otg_enabled;
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uint32_t blank_enabled;
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uint32_t vertical_interrupt1_en;
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uint32_t vertical_interrupt1_line;
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uint32_t vertical_interrupt2_en;
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uint32_t vertical_interrupt2_line;
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};
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void optc1_read_otg_state(struct optc *optc1,
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struct dcn_otg_state *s);
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bool optc1_get_hw_timing(struct timing_generator *tg,
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struct dc_crtc_timing *hw_crtc_timing);
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bool optc1_validate_timing(
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struct timing_generator *optc,
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const struct dc_crtc_timing *timing);
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void optc1_program_timing(
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struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing,
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int vready_offset,
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int vstartup_start,
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int vupdate_offset,
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int vupdate_width,
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const enum signal_type signal,
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bool use_vbios);
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void optc1_setup_vertical_interrupt0(
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struct timing_generator *optc,
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uint32_t start_line,
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uint32_t end_line);
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void optc1_setup_vertical_interrupt1(
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struct timing_generator *optc,
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uint32_t start_line);
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void optc1_setup_vertical_interrupt2(
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struct timing_generator *optc,
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uint32_t start_line);
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void optc1_program_global_sync(
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struct timing_generator *optc,
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int vready_offset,
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int vstartup_start,
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int vupdate_offset,
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int vupdate_width);
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bool optc1_disable_crtc(struct timing_generator *optc);
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bool optc1_is_counter_moving(struct timing_generator *optc);
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void optc1_get_position(struct timing_generator *optc,
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struct crtc_position *position);
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uint32_t optc1_get_vblank_counter(struct timing_generator *optc);
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void optc1_get_crtc_scanoutpos(
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struct timing_generator *optc,
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uint32_t *v_blank_start,
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uint32_t *v_blank_end,
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uint32_t *h_position,
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uint32_t *v_position);
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void optc1_set_early_control(
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struct timing_generator *optc,
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uint32_t early_cntl);
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void optc1_wait_for_state(struct timing_generator *optc,
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enum crtc_state state);
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void optc1_set_blank(struct timing_generator *optc,
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bool enable_blanking);
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bool optc1_is_blanked(struct timing_generator *optc);
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void optc1_program_blank_color(
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struct timing_generator *optc,
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const struct tg_color *black_color);
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bool optc1_did_triggered_reset_occur(
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struct timing_generator *optc);
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void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);
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void optc1_disable_reset_trigger(struct timing_generator *optc);
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void optc1_lock(struct timing_generator *optc);
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void optc1_unlock(struct timing_generator *optc);
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void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
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void optc1_set_drr(
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struct timing_generator *optc,
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const struct drr_params *params);
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void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
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void optc1_set_static_screen_control(
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struct timing_generator *optc,
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uint32_t event_triggers,
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uint32_t num_frames);
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void optc1_program_stereo(struct timing_generator *optc,
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const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
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bool optc1_is_stereo_left_eye(struct timing_generator *optc);
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void optc1_clear_optc_underflow(struct timing_generator *optc);
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void optc1_tg_init(struct timing_generator *optc);
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bool optc1_is_tg_enabled(struct timing_generator *optc);
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bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);
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void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
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void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);
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bool optc1_get_otg_active_size(struct timing_generator *optc,
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uint32_t *otg_active_width,
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uint32_t *otg_active_height);
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void optc1_enable_crtc_reset(
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struct timing_generator *optc,
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int source_tg_inst,
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struct crtc_trigger_info *crtc_tp);
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bool optc1_configure_crc(struct timing_generator *optc,
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const struct crc_params *params);
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bool optc1_get_crc(struct timing_generator *optc,
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uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
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bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
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void optc1_set_vtg_params(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
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#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
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219
drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
Normal file
219
drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
Normal file
@ -0,0 +1,219 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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/**
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* DOC: overview
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*
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* Output Pipe Timing Combiner (OPTC) includes two major functional blocks:
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* Output Data Mapper (ODM) and Output Timing Generator (OTG).
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*
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* - ODM: It is Output Data Mapping block. It can combine input data from
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* multiple OPP data pipes into one single data stream or split data from one
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* OPP data pipe into multiple data streams or just bypass OPP data to DIO.
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* - OTG: It is Output Timing Generator. It generates display timing signals to
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* drive the display output.
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*/
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#ifndef __DC_OPTC_H__
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#define __DC_OPTC_H__
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#include "timing_generator.h"
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struct optc {
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struct timing_generator base;
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const struct dcn_optc_registers *tg_regs;
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const struct dcn_optc_shift *tg_shift;
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const struct dcn_optc_mask *tg_mask;
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int opp_count;
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uint32_t max_h_total;
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uint32_t max_v_total;
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uint32_t min_h_blank;
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uint32_t min_h_sync_width;
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uint32_t min_v_sync_width;
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uint32_t min_v_blank;
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uint32_t min_v_blank_interlace;
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int vstartup_start;
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int vupdate_offset;
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int vupdate_width;
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int vready_offset;
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struct dc_crtc_timing orginal_patched_timing;
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enum signal_type signal;
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};
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struct dcn_otg_state {
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uint32_t v_blank_start;
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uint32_t v_blank_end;
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uint32_t v_sync_a_pol;
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uint32_t v_total;
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uint32_t v_total_max;
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uint32_t v_total_min;
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uint32_t v_total_min_sel;
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uint32_t v_total_max_sel;
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uint32_t v_sync_a_start;
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uint32_t v_sync_a_end;
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uint32_t h_blank_start;
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uint32_t h_blank_end;
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uint32_t h_sync_a_start;
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uint32_t h_sync_a_end;
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uint32_t h_sync_a_pol;
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uint32_t h_total;
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uint32_t underflow_occurred_status;
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uint32_t otg_enabled;
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uint32_t blank_enabled;
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uint32_t vertical_interrupt1_en;
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uint32_t vertical_interrupt1_line;
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uint32_t vertical_interrupt2_en;
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uint32_t vertical_interrupt2_line;
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};
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void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s);
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bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing);
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bool optc1_validate_timing(struct timing_generator *optc,
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const struct dc_crtc_timing *timing);
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void optc1_program_timing(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing,
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int vready_offset,
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int vstartup_start,
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int vupdate_offset,
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int vupdate_width,
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const enum signal_type signal,
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bool use_vbios);
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void optc1_setup_vertical_interrupt0(struct timing_generator *optc,
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uint32_t start_line,
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uint32_t end_line);
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void optc1_setup_vertical_interrupt1(struct timing_generator *optc,
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uint32_t start_line);
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void optc1_setup_vertical_interrupt2(struct timing_generator *optc,
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uint32_t start_line);
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void optc1_program_global_sync(struct timing_generator *optc,
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int vready_offset,
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int vstartup_start,
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int vupdate_offset,
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int vupdate_width);
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bool optc1_disable_crtc(struct timing_generator *optc);
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bool optc1_is_counter_moving(struct timing_generator *optc);
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void optc1_get_position(struct timing_generator *optc,
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struct crtc_position *position);
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uint32_t optc1_get_vblank_counter(struct timing_generator *optc);
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void optc1_get_crtc_scanoutpos(struct timing_generator *optc,
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uint32_t *v_blank_start,
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uint32_t *v_blank_end,
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uint32_t *h_position,
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uint32_t *v_position);
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void optc1_set_early_control(struct timing_generator *optc,
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uint32_t early_cntl);
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void optc1_wait_for_state(struct timing_generator *optc,
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enum crtc_state state);
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void optc1_set_blank(struct timing_generator *optc,
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bool enable_blanking);
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bool optc1_is_blanked(struct timing_generator *optc);
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void optc1_program_blank_color(struct timing_generator *optc,
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const struct tg_color *black_color);
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bool optc1_did_triggered_reset_occur(struct timing_generator *optc);
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void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);
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void optc1_disable_reset_trigger(struct timing_generator *optc);
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void optc1_lock(struct timing_generator *optc);
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void optc1_unlock(struct timing_generator *optc);
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void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
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void optc1_set_drr(struct timing_generator *optc,
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const struct drr_params *params);
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void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
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void optc1_set_static_screen_control(struct timing_generator *optc,
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uint32_t event_triggers,
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uint32_t num_frames);
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void optc1_program_stereo(struct timing_generator *optc,
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const struct dc_crtc_timing *timing,
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struct crtc_stereo_flags *flags);
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bool optc1_is_stereo_left_eye(struct timing_generator *optc);
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void optc1_clear_optc_underflow(struct timing_generator *optc);
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void optc1_tg_init(struct timing_generator *optc);
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bool optc1_is_tg_enabled(struct timing_generator *optc);
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bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);
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void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
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void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);
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bool optc1_get_otg_active_size(struct timing_generator *optc,
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uint32_t *otg_active_width,
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uint32_t *otg_active_height);
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void optc1_enable_crtc_reset(struct timing_generator *optc,
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int source_tg_inst,
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struct crtc_trigger_info *crtc_tp);
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bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params);
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bool optc1_get_crc(struct timing_generator *optc,
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uint32_t *r_cr,
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uint32_t *g_y,
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uint32_t *b_cb);
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bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
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void optc1_set_vtg_params(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing,
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bool program_fp2);
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#endif
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