soundwire: intel: introduce shim and alh base
shim base and alh base are platform-dependent. Adding these two parameters allows us to use different shim/alh base for each platform. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Acked-By: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210723115451.7245-7-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
parent
198fa4bcf6
commit
60e9feb781
@ -63,8 +63,8 @@ static struct sdw_intel_link_dev *intel_link_dev_register(struct sdw_intel_res *
|
|||||||
link->mmio_base = res->mmio_base;
|
link->mmio_base = res->mmio_base;
|
||||||
link->registers = res->mmio_base + SDW_LINK_BASE
|
link->registers = res->mmio_base + SDW_LINK_BASE
|
||||||
+ (SDW_LINK_SIZE * link_id);
|
+ (SDW_LINK_SIZE * link_id);
|
||||||
link->shim = res->mmio_base + SDW_SHIM_BASE;
|
link->shim = res->mmio_base + res->shim_base;
|
||||||
link->alh = res->mmio_base + SDW_ALH_BASE;
|
link->alh = res->mmio_base + res->alh_base;
|
||||||
|
|
||||||
link->ops = res->ops;
|
link->ops = res->ops;
|
||||||
link->dev = res->dev;
|
link->dev = res->dev;
|
||||||
@ -214,6 +214,8 @@ static struct sdw_intel_ctx
|
|||||||
}
|
}
|
||||||
|
|
||||||
ctx->mmio_base = res->mmio_base;
|
ctx->mmio_base = res->mmio_base;
|
||||||
|
ctx->shim_base = res->shim_base;
|
||||||
|
ctx->alh_base = res->alh_base;
|
||||||
ctx->link_mask = res->link_mask;
|
ctx->link_mask = res->link_mask;
|
||||||
ctx->handle = res->handle;
|
ctx->handle = res->handle;
|
||||||
mutex_init(&ctx->shim_lock);
|
mutex_init(&ctx->shim_lock);
|
||||||
@ -302,7 +304,7 @@ sdw_intel_startup_controller(struct sdw_intel_ctx *ctx)
|
|||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
/* Check SNDWLCAP.LCOUNT */
|
/* Check SNDWLCAP.LCOUNT */
|
||||||
caps = ioread32(ctx->mmio_base + SDW_SHIM_BASE + SDW_SHIM_LCAP);
|
caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP);
|
||||||
caps &= GENMASK(2, 0);
|
caps &= GENMASK(2, 0);
|
||||||
|
|
||||||
/* Check HW supported vs property value */
|
/* Check HW supported vs property value */
|
||||||
|
@ -195,6 +195,8 @@ struct sdw_intel_slave_id {
|
|||||||
* @link_list: list to handle interrupts across all links
|
* @link_list: list to handle interrupts across all links
|
||||||
* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
|
* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
|
||||||
* @shim_mask: flags to track initialization of SHIM shared registers
|
* @shim_mask: flags to track initialization of SHIM shared registers
|
||||||
|
* @shim_base: sdw shim base.
|
||||||
|
* @alh_base: sdw alh base.
|
||||||
*/
|
*/
|
||||||
struct sdw_intel_ctx {
|
struct sdw_intel_ctx {
|
||||||
int count;
|
int count;
|
||||||
@ -207,6 +209,8 @@ struct sdw_intel_ctx {
|
|||||||
struct list_head link_list;
|
struct list_head link_list;
|
||||||
struct mutex shim_lock; /* lock for access to shared SHIM registers */
|
struct mutex shim_lock; /* lock for access to shared SHIM registers */
|
||||||
u32 shim_mask;
|
u32 shim_mask;
|
||||||
|
u32 shim_base;
|
||||||
|
u32 alh_base;
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
@ -225,6 +229,8 @@ struct sdw_intel_ctx {
|
|||||||
* machine-specific quirks are handled in the DSP driver.
|
* machine-specific quirks are handled in the DSP driver.
|
||||||
* @clock_stop_quirks: mask array of possible behaviors requested by the
|
* @clock_stop_quirks: mask array of possible behaviors requested by the
|
||||||
* DSP driver. The quirks are common for all links for now.
|
* DSP driver. The quirks are common for all links for now.
|
||||||
|
* @shim_base: sdw shim base.
|
||||||
|
* @alh_base: sdw alh base.
|
||||||
*/
|
*/
|
||||||
struct sdw_intel_res {
|
struct sdw_intel_res {
|
||||||
int count;
|
int count;
|
||||||
@ -236,6 +242,8 @@ struct sdw_intel_res {
|
|||||||
struct device *dev;
|
struct device *dev;
|
||||||
u32 link_mask;
|
u32 link_mask;
|
||||||
u32 clock_stop_quirks;
|
u32 clock_stop_quirks;
|
||||||
|
u32 shim_base;
|
||||||
|
u32 alh_base;
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -166,6 +166,8 @@ static int hda_sdw_probe(struct snd_sof_dev *sdev)
|
|||||||
memset(&res, 0, sizeof(res));
|
memset(&res, 0, sizeof(res));
|
||||||
|
|
||||||
res.mmio_base = sdev->bar[HDA_DSP_BAR];
|
res.mmio_base = sdev->bar[HDA_DSP_BAR];
|
||||||
|
res.shim_base = hdev->desc->sdw_shim_base;
|
||||||
|
res.alh_base = hdev->desc->sdw_alh_base;
|
||||||
res.irq = sdev->ipc_irq;
|
res.irq = sdev->ipc_irq;
|
||||||
res.handle = hdev->info.handle;
|
res.handle = hdev->info.handle;
|
||||||
res.parent = sdev->dev;
|
res.parent = sdev->dev;
|
||||||
|
Loading…
x
Reference in New Issue
Block a user