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drm/amd/display: Only define DP 2.0 symbols if not already defined

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[Why]
For some reason we're defining DP 2.0 definitions inside our
driver. Now that patches to introduce relevant definitions
are slated to be merged into drm-next this is causing conflicts.

In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
        ^
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
        ^
1 error generated.

[How]
Guard all display driver defines with #ifndef for now. Once we pull
in the new definitions into amd-staging-drm-next we will follow
up and drop definitions from our driver and provide follow-up
header updates for any addition DP 2.0 definitions required
by our driver.

We also ensure drm_dp_helper.h is included before dc_dp_types.h.

v3: Ensure drm_dp_helper.h is included before dc_dp_types.h

v2: Add one missing endif

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2021-09-22 13:17:28 -04:00 committed by Alex Deucher
parent c749094923
commit 6131538b49
2 changed files with 50 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
View File

@ -860,28 +860,72 @@ struct psr_caps {
};
#if defined(CONFIG_DRM_AMD_DC_DCN)
#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
#define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006
#endif
#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
#endif
#ifndef DP_FEC_CAPABILITY_1
#define DP_FEC_CAPABILITY_1 0x091
#endif
#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
#endif
#ifndef DP_DSC_CONFIGURATION
#define DP_DSC_CONFIGURATION 0x161
#endif
#ifndef DP_PHY_SQUARE_PATTERN
#define DP_PHY_SQUARE_PATTERN 0x249
#endif
#ifndef DP_128b_132b_SUPPORTED_LINK_RATES
#define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215
#endif
#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216
#endif
#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230
#endif
#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250
#endif
#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260
#endif
#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270
# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
# define DP_DSC_DECODER_COUNT_SHIFT 5
#endif
#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
#endif
#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
#endif
#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
#endif
#ifndef DP_DSC_DECODER_COUNT_MASK
#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
#endif
#ifndef DP_DSC_DECODER_COUNT_SHIFT
#define DP_DSC_DECODER_COUNT_SHIFT 5
#endif
#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
#endif
#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
#endif
#ifndef DP_PHY_REPEATER_128b_132b_RATES
#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
#endif
#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
#endif
#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
#endif
/* TODO - Use DRM header to replace above once available */
union dp_main_line_channel_coding_cap {

1
drivers/gpu/drm/amd/display/dc/os_types.h
View File

@ -35,6 +35,7 @@
#include <asm/byteorder.h>
#include <drm/drm_print.h>
#include <drm/drm_dp_helper.h>
#include "cgs_common.h"