drm/amd/pm: revise the performance level setting APIs
Avoid cross callings which make lock protection enforcement on amdgpu_dpm_force_performance_level() impossible. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -268,7 +268,6 @@ enum amd_dpm_forced_level;
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* @set_clockgating_state: enable/disable cg for the IP block
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* @set_powergating_state: enable/disable pg for the IP block
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* @get_clockgating_state: get current clockgating status
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* @enable_umd_pstate: enable UMD powerstate
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*
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* These hooks provide an interface for controlling the operational state
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* of IP blocks. After acquiring a list of IP blocks for the GPU in use,
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@ -299,7 +298,6 @@ struct amd_ip_funcs {
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int (*set_powergating_state)(void *handle,
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enum amd_powergating_state state);
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void (*get_clockgating_state)(void *handle, u32 *flags);
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int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level);
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};
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@ -300,6 +300,10 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
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struct amdgpu_device *adev = drm_to_adev(ddev);
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enum amd_dpm_forced_level level;
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enum amd_dpm_forced_level current_level;
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uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
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int ret = 0;
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if (amdgpu_in_reset(adev))
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@ -354,10 +358,7 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
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}
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/* profile_exit setting is valid only when current mode is in profile mode */
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if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
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if (!(current_level & profile_mode_mask) &&
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(level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
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pr_err("Currently not in any profile mode!\n");
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pm_runtime_mark_last_busy(ddev->dev);
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@ -365,6 +366,26 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
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return -EINVAL;
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}
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if (!(current_level & profile_mode_mask) &&
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(level & profile_mode_mask)) {
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/* enter UMD Pstate */
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amdgpu_device_ip_set_powergating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_UNGATE);
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amdgpu_device_ip_set_clockgating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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} else if ((current_level & profile_mode_mask) &&
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!(level & profile_mode_mask)) {
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/* exit UMD Pstate */
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amdgpu_device_ip_set_clockgating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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amdgpu_device_ip_set_powergating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_GATE);
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}
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if (amdgpu_dpm_force_performance_level(adev, level)) {
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pm_runtime_mark_last_busy(ddev->dev);
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pm_runtime_put_autosuspend(ddev->dev);
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@ -953,6 +953,7 @@ restart_search:
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static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
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{
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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struct amdgpu_ps *ps;
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enum amd_pm_state_type dpm_state;
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int ret;
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@ -976,7 +977,7 @@ static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
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else
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return -EINVAL;
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if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
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if (amdgpu_dpm == 1 && pp_funcs->print_power_state) {
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printk("switching from power state:\n");
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amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
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printk("switching to power state:\n");
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@ -985,14 +986,14 @@ static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
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/* update whether vce is active */
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ps->vce_active = adev->pm.dpm.vce_active;
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if (adev->powerplay.pp_funcs->display_configuration_changed)
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if (pp_funcs->display_configuration_changed)
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amdgpu_dpm_display_configuration_changed(adev);
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ret = amdgpu_dpm_pre_set_power_state(adev);
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if (ret)
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return ret;
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if (adev->powerplay.pp_funcs->check_state_equal) {
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if (pp_funcs->check_state_equal) {
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if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
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equal = false;
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}
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@ -1000,24 +1001,24 @@ static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
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if (equal)
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return 0;
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if (adev->powerplay.pp_funcs->set_power_state)
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adev->powerplay.pp_funcs->set_power_state(adev->powerplay.pp_handle);
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if (pp_funcs->set_power_state)
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pp_funcs->set_power_state(adev->powerplay.pp_handle);
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amdgpu_dpm_post_set_power_state(adev);
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adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
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adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
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if (adev->powerplay.pp_funcs->force_performance_level) {
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if (pp_funcs->force_performance_level) {
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if (adev->pm.dpm.thermal_active) {
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enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
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/* force low perf level for thermal */
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amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
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pp_funcs->force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
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/* save the user's level */
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adev->pm.dpm.forced_level = level;
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} else {
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/* otherwise, user selected level */
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amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
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pp_funcs->force_performance_level(adev, adev->pm.dpm.forced_level);
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}
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}
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@ -323,12 +323,6 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
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if (*level & profile_mode_mask) {
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hwmgr->saved_dpm_level = hwmgr->dpm_level;
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hwmgr->en_umd_pstate = true;
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amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_UNGATE);
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amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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}
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} else {
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/* exit umd pstate, restore level, enable gfx cg*/
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@ -336,12 +330,6 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
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if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
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*level = hwmgr->saved_dpm_level;
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hwmgr->en_umd_pstate = false;
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amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_GATE);
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}
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}
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}
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@ -1677,14 +1677,7 @@ static int smu_enable_umd_pstate(void *handle,
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/* enter umd pstate, save current level, disable gfx cg*/
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if (*level & profile_mode_mask) {
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smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
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smu_dpm_ctx->enable_umd_pstate = true;
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smu_gpo_control(smu, false);
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amdgpu_device_ip_set_powergating_state(smu->adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_UNGATE);
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amdgpu_device_ip_set_clockgating_state(smu->adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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smu_gfx_ulv_control(smu, false);
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smu_deep_sleep_control(smu, false);
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amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
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@ -1694,16 +1687,9 @@ static int smu_enable_umd_pstate(void *handle,
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if (!(*level & profile_mode_mask)) {
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if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
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*level = smu_dpm_ctx->saved_dpm_level;
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smu_dpm_ctx->enable_umd_pstate = false;
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amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
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smu_deep_sleep_control(smu, true);
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smu_gfx_ulv_control(smu, true);
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amdgpu_device_ip_set_clockgating_state(smu->adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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amdgpu_device_ip_set_powergating_state(smu->adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_GATE);
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smu_gpo_control(smu, true);
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}
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}
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@ -2149,7 +2135,6 @@ const struct amd_ip_funcs smu_ip_funcs = {
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.soft_reset = NULL,
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.set_clockgating_state = smu_set_clockgating_state,
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.set_powergating_state = smu_set_powergating_state,
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.enable_umd_pstate = smu_enable_umd_pstate,
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};
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const struct amdgpu_ip_block_version smu_v11_0_ip_block =
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@ -363,7 +363,6 @@ struct smu_dpm_context {
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uint32_t dpm_context_size;
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void *dpm_context;
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void *golden_dpm_context;
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bool enable_umd_pstate;
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enum amd_dpm_forced_level dpm_level;
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enum amd_dpm_forced_level saved_dpm_level;
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enum amd_dpm_forced_level requested_dpm_level;
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