Merge remote branch 'keithp/drm-intel-fixes' of /ssd/git/drm-next into drm-fixes
* 'keithp/drm-intel-fixes' of /ssd/git/drm-next: drm/i915: Reset GMBUS controller after NAK drm/i915: Busy-spin wait_for condition in atomic contexts drm/i915/lvds: Always return connected in the absence of better information
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commit
61df611d5e
@ -39,7 +39,7 @@
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ret__ = -ETIMEDOUT; \
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ret__ = -ETIMEDOUT; \
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break; \
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break; \
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} \
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} \
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if (W && !in_dbg_master()) msleep(W); \
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if (W && !(in_atomic() || in_dbg_master())) msleep(W); \
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} \
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} \
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ret__; \
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ret__; \
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})
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})
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@ -259,7 +259,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
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if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
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if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
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goto timeout;
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goto timeout;
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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return 0;
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goto clear_err;
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val = I915_READ(GMBUS3 + reg_offset);
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val = I915_READ(GMBUS3 + reg_offset);
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do {
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do {
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@ -287,7 +287,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
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if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
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if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
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goto timeout;
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goto timeout;
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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return 0;
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goto clear_err;
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val = loop = 0;
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val = loop = 0;
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do {
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do {
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@ -302,14 +302,31 @@ gmbus_xfer(struct i2c_adapter *adapter,
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if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
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if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
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goto timeout;
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goto timeout;
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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return 0;
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goto clear_err;
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}
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}
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return num;
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goto done;
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clear_err:
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/* Toggle the Software Clear Interrupt bit. This has the effect
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* of resetting the GMBUS controller and so clearing the
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* BUS_ERROR raised by the slave's NAK.
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*/
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I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
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I915_WRITE(GMBUS1 + reg_offset, 0);
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done:
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/* Mark the GMBUS interface as disabled. We will re-enable it at the
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* start of the next xfer, till then let it sleep.
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*/
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I915_WRITE(GMBUS0 + reg_offset, 0);
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return i;
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timeout:
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timeout:
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DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
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DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
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bus->reg0 & 0xff, bus->adapter.name);
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bus->reg0 & 0xff, bus->adapter.name);
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I915_WRITE(GMBUS0 + reg_offset, 0);
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/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
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/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
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bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
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bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
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if (!bus->force_bit)
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if (!bus->force_bit)
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@ -473,19 +473,13 @@ static enum drm_connector_status
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intel_lvds_detect(struct drm_connector *connector, bool force)
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intel_lvds_detect(struct drm_connector *connector, bool force)
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{
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{
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struct drm_device *dev = connector->dev;
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struct drm_device *dev = connector->dev;
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enum drm_connector_status status = connector_status_connected;
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enum drm_connector_status status;
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status = intel_panel_detect(dev);
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status = intel_panel_detect(dev);
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if (status != connector_status_unknown)
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if (status != connector_status_unknown)
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return status;
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return status;
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/* ACPI lid methods were generally unreliable in this generation, so
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return connector_status_connected;
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* don't even bother.
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*/
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if (IS_GEN2(dev) || IS_GEN3(dev))
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return connector_status_connected;
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return status;
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}
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}
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/**
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/**
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