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drm/amd/pp: Fix sysfs pp_dpm_pcie bug on CI/VI

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when echo "01">pp_dpm_pcie
the pcie dpm will fix in highest link speed.
But user should expect auto speed between
level 0 and level1

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-01-25 18:42:08 +08:00 committed by Alex Deucher
parent 337ecd6a98
commit 61e208b16e
2 changed files with 20 additions and 14 deletions
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15
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
View File

@ -6642,6 +6642,9 @@ static int ci_dpm_force_clock_level(void *handle,
if (adev->pm.dpm.forced_level != AMD_DPM_FORCED_LEVEL_MANUAL) if (adev->pm.dpm.forced_level != AMD_DPM_FORCED_LEVEL_MANUAL)
return -EINVAL; return -EINVAL;
if (mask == 0)
return -EINVAL;
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
if (!pi->sclk_dpm_key_disabled) if (!pi->sclk_dpm_key_disabled)
@ -6660,15 +6663,15 @@ static int ci_dpm_force_clock_level(void *handle,
case PP_PCIE: case PP_PCIE:
{ {
uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask; uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
uint32_t level = 0;
while (tmp >>= 1) if (!pi->pcie_dpm_key_disabled) {
level++; if (fls(tmp) != ffs(tmp))
amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_UnForceLevel);
if (!pi->pcie_dpm_key_disabled) else
amdgpu_ci_send_msg_to_smc_with_parameter(adev, amdgpu_ci_send_msg_to_smc_with_parameter(adev,
PPSMC_MSG_PCIeDPM_ForceLevel, PPSMC_MSG_PCIeDPM_ForceLevel,
level); fls(tmp) - 1);
}
break; break;
} }
default: default:

15
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -4296,6 +4296,9 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
{ {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (mask == 0)
return -EINVAL;
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
if (!data->sclk_dpm_key_disabled) if (!data->sclk_dpm_key_disabled)
@ -4312,15 +4315,15 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
case PP_PCIE: case PP_PCIE:
{ {
uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
uint32_t level = 0;
while (tmp >>= 1) if (!data->pcie_dpm_key_disabled) {
level++; if (fls(tmp) != ffs(tmp))
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel);
if (!data->pcie_dpm_key_disabled) else
smum_send_msg_to_smc_with_parameter(hwmgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PCIeDPM_ForceLevel, PPSMC_MSG_PCIeDPM_ForceLevel,
level); fls(tmp) - 1);
}
break; break;
} }
default: default: