MIPS changes for 4.16-rc2
A single change (and associated DT binding update) to allow the address of the MIPS Cluster Power Controller (CPC) to be chosen by DT, which allows SMP to work on generic MIPS kernels where the bootloader hasn't configured the CPC address (i.e. the new Ranchu platform). -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEd80NauSabkiESfLYbAtpk944dnoFAlqCxagACgkQbAtpk944 dnqc5g//Ss6wWO2hgUtzUTEwPgmCLANG1cVvykI0a1rROzdnEUI8CRUoiRlD0A0B gxpDZKNXWkpZ1veL7XuwKjFLk1tW7a/MNB/nxIPhruGRl1uBH8BOo3OXYE/ZzvKl 74kN55Ykz4sltlyuTSSG/6e41ysXkSB4xJdTb/hx6jPOVwFM4RoOFODmhRYf5mKO p9N9ZYpqC07IYL6upRqEhEG1LePio3aVx66ngq+d+8SOISMP3puXf5TkvRFkkCfz OSPsvDtbsm8tf1yM4vvw7PNK4JsuS+OjbDMaLZXZFy+OBMAb0VJ2ZCG9OM5Chkvc Dqkb5Ds0pB0kYGHL8bh726q5NmcIVfKT5k0XRyz5a3weHdSbCn5/pHPg5uxtvlDP xt2i6k3HJjoMb5FmbhObROf6O904d5vi4u0E17EefWOwEaDn23PruzqUDqAGgq4g k84hXuVSZd/Ymu/9Lh+KYlhyiqCKcReleIRzg+ySU5bmXZR8izkiTdU1NIXRH4mg 4xi7SV/tygACd0cu42CF6b5lOWIGBZZ5qtyI93cfWRCngL2LT0rYfCNg+IuuK9eb hZ2YZ7AjqUWYMPQgxHJ6rPLslY9/LDiW3OrtL7/3gEQyC3D41XYSIFThMO+DDC5c Ok6nJNxnEE3AvqE5iHjr/PA3GRx6bUmv/2Ty+DzDqWnO7Gayxls= =E7mu -----END PGP SIGNATURE----- Merge tag 'mips_4.16_2' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips Pull MIPS fix from James Hogan: "A single change (and associated DT binding update) to allow the address of the MIPS Cluster Power Controller (CPC) to be chosen by DT, which allows SMP to work on generic MIPS kernels where the bootloader hasn't configured the CPC address (i.e. the new Ranchu platform)" * tag 'mips_4.16_2' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: MIPS: CPC: Map registers using DT in mips_cpc_default_phys_base() dt-bindings: Document mti,mips-cpc binding
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Documentation/devicetree/bindings/power/mti,mips-cpc.txt
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Documentation/devicetree/bindings/power/mti,mips-cpc.txt
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@ -0,0 +1,8 @@
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Binding for MIPS Cluster Power Controller (CPC).
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This binding allows a system to specify where the CPC registers are
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located.
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Required properties:
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compatible : Should be "mti,mips-cpc".
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regs: Should describe the address & size of the CPC register region.
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@ -9206,6 +9206,7 @@ MIPS GENERIC PLATFORM
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M: Paul Burton <paul.burton@mips.com>
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L: linux-mips@linux-mips.org
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S: Supported
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F: Documentation/devicetree/bindings/power/mti,mips-cpc.txt
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F: arch/mips/generic/
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F: arch/mips/tools/generic-board-config.sh
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@ -10,6 +10,8 @@
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#include <linux/errno.h>
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#include <linux/percpu.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/spinlock.h>
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#include <asm/mips-cps.h>
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@ -22,6 +24,17 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
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phys_addr_t __weak mips_cpc_default_phys_base(void)
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{
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struct device_node *cpc_node;
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struct resource res;
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int err;
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cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc");
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if (cpc_node) {
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err = of_address_to_resource(cpc_node, 0, &res);
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if (!err)
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return res.start;
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}
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return 0;
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}
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