phy: ti-pipe3: Add SATA DPLL support
USB and SATA DPLLs need different settings. Provide the SATA DPLL settings and use the proper DPLL settings based on device tree node's compatible_id. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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1562864f0f
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@ -66,6 +66,11 @@ struct pipe3_dpll_params {
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u32 mf;
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};
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struct pipe3_dpll_map {
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unsigned long rate;
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struct pipe3_dpll_params params;
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};
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struct ti_pipe3 {
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void __iomem *pll_ctrl_base;
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struct device *dev;
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@ -73,20 +78,27 @@ struct ti_pipe3 {
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struct clk *wkupclk;
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struct clk *sys_clk;
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struct clk *refclk;
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struct pipe3_dpll_map *dpll_map;
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};
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struct pipe3_dpll_map {
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unsigned long rate;
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struct pipe3_dpll_params params;
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};
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static struct pipe3_dpll_map dpll_map[] = {
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static struct pipe3_dpll_map dpll_map_usb[] = {
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{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
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{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
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{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
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{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
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{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
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{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
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{ }, /* Terminator */
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};
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static struct pipe3_dpll_map dpll_map_sata[] = {
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{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
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{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
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{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
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{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
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{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
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{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
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{ }, /* Terminator */
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};
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static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
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@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
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__raw_writel(data, addr + offset);
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}
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static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
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static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
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{
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int i;
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unsigned long rate;
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struct pipe3_dpll_map *dpll_map = phy->dpll_map;
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for (i = 0; i < ARRAY_SIZE(dpll_map); i++) {
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if (rate == dpll_map[i].rate)
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return &dpll_map[i].params;
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rate = clk_get_rate(phy->sys_clk);
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for (; dpll_map->rate; dpll_map++) {
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if (rate == dpll_map->rate)
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return &dpll_map->params;
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}
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dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
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return NULL;
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}
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@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
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static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
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{
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u32 val;
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unsigned long rate;
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struct pipe3_dpll_params *dpll_params;
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rate = clk_get_rate(phy->sys_clk);
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dpll_params = ti_pipe3_get_dpll_params(rate);
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if (!dpll_params) {
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dev_err(phy->dev,
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"No DPLL configuration for %lu Hz SYS CLK\n", rate);
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dpll_params = ti_pipe3_get_dpll_params(phy);
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if (!dpll_params)
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return -EINVAL;
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}
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val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGN_MASK;
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@ -244,6 +256,10 @@ static struct phy_ops ops = {
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.owner = THIS_MODULE,
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};
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#ifdef CONFIG_OF
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static const struct of_device_id ti_pipe3_id_table[];
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#endif
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static int ti_pipe3_probe(struct platform_device *pdev)
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{
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struct ti_pipe3 *phy;
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@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
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struct device_node *node = pdev->dev.of_node;
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struct device_node *control_node;
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struct platform_device *control_pdev;
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const struct of_device_id *match;
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if (!node)
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match = of_match_device(of_match_ptr(ti_pipe3_id_table), &pdev->dev);
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if (!match)
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return -EINVAL;
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phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
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@ -263,6 +281,12 @@ static int ti_pipe3_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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phy->dpll_map = (struct pipe3_dpll_map *)match->data;
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if (!phy->dpll_map) {
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dev_err(&pdev->dev, "no DPLL data\n");
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return -EINVAL;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
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phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(phy->pll_ctrl_base))
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@ -388,8 +412,18 @@ static const struct dev_pm_ops ti_pipe3_pm_ops = {
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#ifdef CONFIG_OF
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static const struct of_device_id ti_pipe3_id_table[] = {
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{ .compatible = "ti,phy-usb3" },
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{ .compatible = "ti,omap-usb3" },
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{
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.compatible = "ti,phy-usb3",
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.data = dpll_map_usb,
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},
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{
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.compatible = "ti,omap-usb3",
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.data = dpll_map_usb,
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},
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{
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.compatible = "ti,phy-pipe3-sata",
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.data = dpll_map_sata,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
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