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drm/i915/cnl: skip PW_DDI_F on certain skus

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The skus guarded by IS_CNL_WITH_PORT_F() have port F and thus they need
those power wells. The others don't have those. Up to now we were
just overriding the number of power wells on !IS_CNL_WITH_PORT_F(),
relying on those power wells to be the last ones. Now that we have logic
in place to skip power wells by id, use it instead.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-2-lucas.demarchi@intel.com
This commit is contained in:
Lucas De Marchi 2020-10-14 12:19:28 -07:00
parent 9ccd24e9b0
commit 62277f33e9
2 changed files with 9 additions and 12 deletions
drivers/gpu/drm/i915/display
intel_display_power.cintel_display_power.h

19
drivers/gpu/drm/i915/display/intel_display_power.c

@ -3650,7 +3650,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DDI F IO power well",
.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
.id = CNL_DISP_PW_DDI_F_IO,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = CNL_PW_CTL_IDX_DDI_F,
@ -3660,7 +3660,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "AUX F",
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
.id = CNL_DISP_PW_DDI_F_AUX,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = CNL_PW_CTL_IDX_AUX_F,
@ -4640,17 +4640,12 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
err = set_power_wells(power_domains, tgl_power_wells);
} else if (IS_GEN(dev_priv, 11)) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
} else if (IS_CNL_WITH_PORT_F(dev_priv)) {
err = set_power_wells(power_domains, cnl_power_wells);
/*
* DDI and Aux IO are getting enabled for all ports
* regardless the presence or use. So, in order to avoid
* timeouts, lets remove them from the list
* for the SKUs without port F.
*/
if (!IS_CNL_WITH_PORT_F(dev_priv))
power_domains->power_well_count -= 2;
} else if (IS_CANNONLAKE(dev_priv)) {
err = set_power_wells_mask(power_domains, cnl_power_wells,
BIT_ULL(CNL_DISP_PW_DDI_F_IO) |
BIT_ULL(CNL_DISP_PW_DDI_F_AUX));
} else if (IS_GEMINILAKE(dev_priv)) {
err = set_power_wells(power_domains, glk_power_wells);
} else if (IS_BROXTON(dev_priv)) {

2
drivers/gpu/drm/i915/display/intel_display_power.h

@ -101,6 +101,8 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
CNL_DISP_PW_DDI_F_IO,
CNL_DISP_PW_DDI_F_AUX,
ICL_DISP_PW_3,
SKL_DISP_DC_OFF,
};