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arm64: dts: qcom: sc7280: Mark some nodes as 'reserved'

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[ Upstream commit 6da24ba932082bae110feb917a64bb54637fa7c0 ]

With the standard Qualcomm TrustZone setup, components such as lpasscc,
pdc_reset and watchdog shouldn't be touched by Linux. Mark them with
the status 'reserved' and reenable them in the chrome-common dtsi.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-1-14bb7cedadf5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stable-dep-of: 6897fac411db ("arm64: dts: qcom: sc7280: Make watchdog bark interrupt edge triggered")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Luca Weiss 2023-09-19 14:45:55 +02:00 committed by Greg Kroah-Hartman
parent 6157194e64
commit 6252b33a31
2 changed files with 31 additions and 1 deletions
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24
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View File

@ -46,6 +46,26 @@
};
};
&lpass_aon {
status = "okay";
};
&lpass_core {
status = "okay";
};
&lpass_hm {
status = "okay";
};
&lpasscc {
status = "okay";
};
&pdc_reset {
status = "okay";
};
/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
&pmk8350_pon {
status = "disabled";
@ -84,6 +104,10 @@
dma-coherent;
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";

8
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -2255,6 +2255,7 @@
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
status = "reserved"; /* Owned by ADSP firmware */
};
lpass_rx_macro: codec@3200000 {
@ -2406,6 +2407,7 @@
clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
#clock-cells = <1>;
#power-domain-cells = <1>;
status = "reserved"; /* Owned by ADSP firmware */
};
lpass_core: clock-controller@3900000 {
@ -2416,6 +2418,7 @@
power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
status = "reserved"; /* Owned by ADSP firmware */
};
lpass_cpu: audio@3987000 {
@ -2486,6 +2489,7 @@
clock-names = "bi_tcxo";
#clock-cells = <1>;
#power-domain-cells = <1>;
status = "reserved"; /* Owned by ADSP firmware */
};
lpass_ag_noc: interconnect@3c40000 {
@ -4199,6 +4203,7 @@
compatible = "qcom,sc7280-pdc-global";
reg = <0 0x0b5e0000 0 0x20000>;
#reset-cells = <1>;
status = "reserved"; /* Owned by firmware */
};
tsens0: thermal-sensor@c263000 {
@ -5195,11 +5200,12 @@
};
};
watchdog@17c10000 {
watchdog: watchdog@17c10000 {
compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
status = "reserved"; /* Owned by Gunyah hyp */
};
timer@17c20000 {