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iio: adc: ad7606: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to reflect the fact DMA safety 'may' require
separate cachelines.

Fixes: 7989b4bb23fe ("iio: adc: ad7616: Add support for AD7616 ADC")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-15-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:55:54 +01:00
parent 58b74555af
commit 6268c6eebb
1 changed files with 2 additions and 2 deletions
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drivers/iio/adc/ad7606.h
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@ -116,11 +116,11 @@ struct ad7606_state {
struct completion completion; struct completion completion;
/* /*
* DMA (thus cache coherency maintenance) requires the * DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines. * transfer buffers to live in their own cache lines.
* 16 * 16-bit samples + 64-bit timestamp * 16 * 16-bit samples + 64-bit timestamp
*/ */
unsigned short data[20] ____cacheline_aligned; unsigned short data[20] __aligned(IIO_DMA_MINALIGN);
__be16 d16[2]; __be16 d16[2];
}; };