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hpt366: HPT36x PCI clock detection fix

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Fix minor coding mistake in the HPT36x PCI clock detection code noticed by
Bartlomiej Zolnierkiewicz -- it always reported 33 MHz due to the missing
'break' statements.  This, however, most probably never mattered -- in fact, I
was thinking of removing the 25/40 MHz cases completely since HPT36x BIOSes
didn't seem to set any other value than 7 into the 'cmd_high_time' field, i.e.
 supported only 33 MHz PCI.

Note that in the original driver there was another bug: 25 and 40 MHz cases
were interchanged.  Since the 'cmd_high_time' field is in units of PCI clocks,
a lower clock count just *cannot* correspond to a higher frequency, i.  e.  it
should be 5 for 25 MHz PCI and 9 for 40 MHz PCI, not the other way around.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Sergei Shtylyov 2007-02-07 18:18:20 +01:00 committed by Bartlomiej Zolnierkiewicz
parent 7b73ee05d0
commit 6273d26a5b
1 changed files with 6 additions and 2 deletions
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8
drivers/ide/pci/hpt366.c
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@ -1,5 +1,5 @@
/* /*
* linux/drivers/ide/pci/hpt366.c Version 1.00 Jun 25, 2006 * linux/drivers/ide/pci/hpt366.c Version 1.01 Dec 23, 2006
* *
* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
* Portions Copyright (C) 2001 Sun Microsystems, Inc. * Portions Copyright (C) 2001 Sun Microsystems, Inc.
@ -107,7 +107,8 @@
* frequency * frequency
* - switch to using the DPLL clock and enable UltraATA/133 mode by default on * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
* anything newer than HPT370/A * anything newer than HPT370/A
* - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(); * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
* also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
* unify HPT36x/37x timing setup code and the speedproc handlers by joining * unify HPT36x/37x timing setup code and the speedproc handlers by joining
* the register setting lists into the table indexed by the clock selected * the register setting lists into the table indexed by the clock selected
* Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
@ -1125,11 +1126,14 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
switch((itr1 >> 8) & 0x07) { switch((itr1 >> 8) & 0x07) {
case 0x09: case 0x09:
pci_clk = 40; pci_clk = 40;
break;
case 0x05: case 0x05:
pci_clk = 25; pci_clk = 25;
break;
case 0x07: case 0x07:
default: default:
pci_clk = 33; pci_clk = 33;
break;
} }
} }