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PCI: qcom: Add SM8550 PCIe support

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SM8550 requires two additional clocks for proper working.

Add these two clocks as optional clocks (as only required by this
platform) and compatible for this platform.

While at it, let's also rename the reset variable to "rst" from
"pci_reset" to match the existing naming preference.

Link: https://lore.kernel.org/r/20230320144658.1794991-2-abel.vesa@linaro.org
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
[lpieralisi@kernel.org: commit log rewording]
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
This commit is contained in:
Abel Vesa 2023-03-20 16:46:58 +02:00 committed by Lorenzo Pieralisi
parent 1a24edc38d
commit 6276a403c0
1 changed files with 14 additions and 11 deletions
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25
drivers/pci/controller/dwc/pcie-qcom.c
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@ -193,13 +193,13 @@ struct qcom_pcie_resources_2_4_0 {
int num_resets; int num_resets;
}; };
#define QCOM_PCIE_2_7_0_MAX_CLOCKS 13 #define QCOM_PCIE_2_7_0_MAX_CLOCKS 15
#define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2
struct qcom_pcie_resources_2_7_0 { struct qcom_pcie_resources_2_7_0 {
struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS];
int num_clks; int num_clks;
struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES];
struct reset_control *pci_reset; struct reset_control *rst;
}; };
#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 #define QCOM_PCIE_2_9_0_MAX_CLOCKS 5
@ -848,9 +848,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
unsigned int idx; unsigned int idx;
int ret; int ret;
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); res->rst = devm_reset_control_array_get_exclusive(dev);
if (IS_ERR(res->pci_reset)) if (IS_ERR(res->rst))
return PTR_ERR(res->pci_reset); return PTR_ERR(res->rst);
res->supplies[0].supply = "vdda"; res->supplies[0].supply = "vdda";
res->supplies[1].supply = "vddpe-3v3"; res->supplies[1].supply = "vddpe-3v3";
@ -876,10 +876,12 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
res->clks[idx++].id = "ddrss_sf_tbu"; res->clks[idx++].id = "ddrss_sf_tbu";
res->clks[idx++].id = "aggre0"; res->clks[idx++].id = "aggre0";
res->clks[idx++].id = "aggre1"; res->clks[idx++].id = "aggre1";
res->clks[idx++].id = "noc_aggr";
res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_4";
res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "noc_aggr_south_sf";
res->clks[idx++].id = "cnoc_qx"; res->clks[idx++].id = "cnoc_qx";
res->clks[idx++].id = "sleep"; res->clks[idx++].id = "sleep";
res->clks[idx++].id = "cnoc_sf_axi";
num_opt_clks = idx - num_clks; num_opt_clks = idx - num_clks;
res->num_clks = idx; res->num_clks = idx;
@ -909,17 +911,17 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
if (ret < 0) if (ret < 0)
goto err_disable_regulators; goto err_disable_regulators;
ret = reset_control_assert(res->pci_reset); ret = reset_control_assert(res->rst);
if (ret < 0) { if (ret) {
dev_err(dev, "cannot assert pci reset\n"); dev_err(dev, "reset assert failed (%d)\n", ret);
goto err_disable_clocks; goto err_disable_clocks;
} }
usleep_range(1000, 1500); usleep_range(1000, 1500);
ret = reset_control_deassert(res->pci_reset); ret = reset_control_deassert(res->rst);
if (ret < 0) { if (ret) {
dev_err(dev, "cannot deassert pci reset\n"); dev_err(dev, "reset deassert failed (%d)\n", ret);
goto err_disable_clocks; goto err_disable_clocks;
} }
@ -1618,6 +1620,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
{ } { }
}; };