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mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode

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The Octal DTR configuration is stored in the CFR5V register. This
register is 1 byte wide. But 1 byte long transactions are not allowed in
8D-8D-8D mode. Since the next byte address does not contain any
register, it is safe to write any value to it. Write a 0 to it.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20210531181757.19458-3-p.yadav@ti.com
This commit is contained in:
Pratyush Yadav 2021-05-31 23:47:53 +05:30 committed by Tudor Ambarus
parent 0d051a4982
commit 63017068a6
1 changed files with 13 additions and 5 deletions
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18
drivers/mtd/spi-nor/spansion.c
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@ -65,10 +65,18 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
if (ret) if (ret)
return ret; return ret;
if (enable) if (enable) {
*buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
else } else {
*buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; /*
* The register is 1-byte wide, but 1-byte transactions are not
* allowed in 8D-8D-8D mode. Since there is no register at the
* next location, just initialize the value to 0 and let the
* transaction go on.
*/
buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
buf[1] = 0;
}
op = (struct spi_mem_op) op = (struct spi_mem_op)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
@ -76,7 +84,7 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
SPINOR_REG_CYPRESS_CFR5V, SPINOR_REG_CYPRESS_CFR5V,
1), 1),
SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(1, buf, 1)); SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
if (!enable) if (!enable)
spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);