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m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPU

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The Pin Assignment register definitions for the ColdFire 54xx CPU family are
inconsistently named and defined compared to the other ColdFire part
definitions. Rename them with the same prefix as used on other parts,
MCFGPIO_PAR_, and make their definitions include the MCF_MBAR periphperal
region offset.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2012-09-18 14:34:04 +10:00
parent 98d9696b38
commit 632306f245
3 changed files with 20 additions and 15 deletions
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21
arch/m68k/include/asm/m54xxsim.h
View File

@ -70,15 +70,25 @@
#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
/*
* Some PSC related definitions
* Pin Assignment register definitions
*/
#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
#define MCF_PAR_SDA (0x0008)
#define MCF_PAR_SCL (0x0004)
#define MCF_PAR_PSC_TXD (0x04)
#define MCF_PAR_PSC_RXD (0x08)
#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
#define MCF_PAR_PSC_CTS_GPIO (0x00)
#define MCF_PAR_PSC_CTS_BCLK (0x80)
#define MCF_PAR_PSC_CTS_CTS (0xC0)
@ -87,7 +97,4 @@
#define MCF_PAR_PSC_RTS_RTS (0x30)
#define MCF_PAR_PSC_CANRX (0x40)
#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */
#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */
#endif /* m54xxsim_h */

10
arch/m68k/platform/coldfire/m54xx.c
View File

@ -30,14 +30,12 @@
static void __init m54xx_uarts_init(void)
{
/* enable io pins */
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
MCF_MBAR + MCF_PAR_PSC(0));
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
MCF_MBAR + MCF_PAR_PSC(1));
MCFGPIO_PAR_PSC1);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2));
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
MCF_MBAR + MCF_PAR_PSC(3));
MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
}
/***************************************************************************/

4
arch/m68k/platform/coldfire/pci.c
View File

@ -272,8 +272,8 @@ static int __init mcf_pci_init(void)
PACR_EXTMINTE(0x1f), PACR);
/* Set required multi-function pins for PCI bus use */
__raw_writew(0x3ff, MCF_PAR_PCIBG);
__raw_writew(0x3ff, MCF_PAR_PCIBR);
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
/* Set up config space for local host bus controller */
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |