clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
This driver manages Reset and Clock of STM32MP13 soc. It uses a clk-stm32-core module to manage stm32 gate, mux and divider for STM32MP13 and for new future soc. All gates, muxes, dividers are identify by an index and information are stored in array (register address, shift, with, flags...) This is useful when we have two clocks with the same gate or when one mux manages two output clocks. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-3-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Gabriel Fernandez
Stephen Boyd
parent
722dc8a1d5
commit
637cee5ffc
@ -368,6 +368,11 @@ config COMMON_CLK_VC5
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This driver supports the IDT VersaClock 5 and VersaClock 6
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programmable clock generators.
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config COMMON_CLK_STM32MP135
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def_bool COMMON_CLK && MACH_STM32MP13
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help
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Support for stm32mp135 SoC family clocks
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config COMMON_CLK_STM32MP157
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def_bool COMMON_CLK && MACH_STM32MP157
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help
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@ -115,6 +115,7 @@ obj-y += socfpga/
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-y += sprd/
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obj-$(CONFIG_ARCH_STI) += st/
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obj-$(CONFIG_ARCH_STM32) += stm32/
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obj-$(CONFIG_SOC_STARFIVE) += starfive/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-y += sunxi-ng/
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1
drivers/clk/stm32/Makefile
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1
drivers/clk/stm32/Makefile
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@ -0,0 +1 @@
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obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o
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93
drivers/clk/stm32/clk-stm32-core.c
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93
drivers/clk/stm32/clk-stm32-core.c
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@ -0,0 +1,93 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "clk-stm32-core.h"
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#include "reset-stm32.h"
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static DEFINE_SPINLOCK(rlock);
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static int stm32_rcc_clock_init(struct device *dev,
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const struct of_device_id *match,
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void __iomem *base)
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{
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const struct stm32_rcc_match_data *data = match->data;
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struct clk_hw_onecell_data *clk_data = data->hw_clks;
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struct device_node *np = dev_of_node(dev);
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struct clk_hw **hws;
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int n, max_binding;
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max_binding = data->maxbinding;
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clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->num = max_binding;
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hws = clk_data->hws;
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for (n = 0; n < max_binding; n++)
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hws[n] = ERR_PTR(-ENOENT);
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for (n = 0; n < data->num_clocks; n++) {
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const struct clock_config *cfg_clock = &data->tab_clocks[n];
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struct clk_hw *hw = ERR_PTR(-ENOENT);
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if (cfg_clock->func)
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hw = (*cfg_clock->func)(dev, data, base, &rlock,
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cfg_clock);
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if (IS_ERR(hw)) {
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dev_err(dev, "Can't register clk %d: %ld\n", n,
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PTR_ERR(hw));
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return PTR_ERR(hw);
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}
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if (cfg_clock->id != NO_ID)
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hws[cfg_clock->id] = hw;
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}
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return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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}
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int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
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void __iomem *base)
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{
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const struct of_device_id *match;
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int err;
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match = of_match_node(match_data, dev_of_node(dev));
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if (!match) {
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dev_err(dev, "match data not found\n");
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return -ENODEV;
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}
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/* RCC Reset Configuration */
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err = stm32_rcc_reset_init(dev, match, base);
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if (err) {
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pr_err("stm32 reset failed to initialize\n");
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return err;
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}
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/* RCC Clock Configuration */
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err = stm32_rcc_clock_init(dev, match, base);
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if (err) {
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pr_err("stm32 clock failed to initialize\n");
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return err;
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}
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return 0;
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}
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92
drivers/clk/stm32/clk-stm32-core.h
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92
drivers/clk/stm32/clk-stm32-core.h
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@ -0,0 +1,92 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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*/
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#include <linux/clk-provider.h>
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struct stm32_rcc_match_data;
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struct stm32_mux_cfg {
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u16 offset;
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u8 shift;
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u8 width;
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u8 flags;
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u32 *table;
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u8 ready;
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};
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struct stm32_gate_cfg {
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u16 offset;
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u8 bit_idx;
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u8 set_clr;
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};
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struct stm32_div_cfg {
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u16 offset;
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u8 shift;
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u8 width;
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u8 flags;
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u8 ready;
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const struct clk_div_table *table;
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};
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struct stm32_composite_cfg {
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int mux;
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int gate;
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int div;
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};
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#define NO_ID 0xFFFFFFFF
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#define NO_STM32_MUX 0xFFFF
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#define NO_STM32_DIV 0xFFFF
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#define NO_STM32_GATE 0xFFFF
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struct clock_config {
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unsigned long id;
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void *clock_cfg;
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struct clk_hw *(*func)(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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spinlock_t *lock,
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const struct clock_config *cfg);
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};
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struct clk_stm32_clock_data {
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u16 *gate_cpt;
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const struct stm32_gate_cfg *gates;
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const struct stm32_mux_cfg *muxes;
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const struct stm32_div_cfg *dividers;
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};
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struct stm32_rcc_match_data {
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struct clk_hw_onecell_data *hw_clks;
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unsigned int num_clocks;
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const struct clock_config *tab_clocks;
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unsigned int maxbinding;
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struct clk_stm32_clock_data *clock_data;
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u32 clear_offset;
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};
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int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
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void __iomem *base);
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int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
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void __iomem *base);
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/* MUX define */
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#define MUX_NO_RDY 0xFF
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/* DIV define */
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#define DIV_NO_RDY 0xFF
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/* Clock registering */
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#define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\
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{\
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.id = (_binding),\
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.clock_cfg = (_struct) {_clk},\
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.func = (_register),\
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}
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520
drivers/clk/stm32/clk-stm32mp13.c
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520
drivers/clk/stm32/clk-stm32mp13.c
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@ -0,0 +1,520 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/stm32mp13-clks.h>
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#include "clk-stm32-core.h"
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#include "stm32mp13_rcc.h"
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#define RCC_CLR_OFFSET 0x4
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/* STM32 Gates definition */
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enum enum_gate_cfg {
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GATE_MCO1,
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GATE_MCO2,
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GATE_DBGCK,
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GATE_TRACECK,
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GATE_DDRC1,
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GATE_DDRC1LP,
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GATE_DDRPHYC,
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GATE_DDRPHYCLP,
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GATE_DDRCAPB,
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GATE_DDRCAPBLP,
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GATE_AXIDCG,
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GATE_DDRPHYCAPB,
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GATE_DDRPHYCAPBLP,
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GATE_TIM2,
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GATE_TIM3,
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GATE_TIM4,
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GATE_TIM5,
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GATE_TIM6,
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GATE_TIM7,
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GATE_LPTIM1,
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GATE_SPI2,
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GATE_SPI3,
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GATE_USART3,
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GATE_UART4,
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GATE_UART5,
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GATE_UART7,
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GATE_UART8,
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GATE_I2C1,
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GATE_I2C2,
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GATE_SPDIF,
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GATE_TIM1,
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GATE_TIM8,
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GATE_SPI1,
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GATE_USART6,
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GATE_SAI1,
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GATE_SAI2,
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GATE_DFSDM,
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GATE_ADFSDM,
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GATE_FDCAN,
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GATE_LPTIM2,
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GATE_LPTIM3,
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GATE_LPTIM4,
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GATE_LPTIM5,
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GATE_VREF,
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GATE_DTS,
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GATE_PMBCTRL,
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GATE_HDP,
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GATE_SYSCFG,
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GATE_DCMIPP,
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GATE_DDRPERFM,
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GATE_IWDG2APB,
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GATE_USBPHY,
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GATE_STGENRO,
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GATE_LTDC,
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GATE_RTCAPB,
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GATE_TZC,
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GATE_ETZPC,
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GATE_IWDG1APB,
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GATE_BSEC,
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GATE_STGENC,
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GATE_USART1,
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GATE_USART2,
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GATE_SPI4,
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GATE_SPI5,
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GATE_I2C3,
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GATE_I2C4,
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GATE_I2C5,
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GATE_TIM12,
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GATE_TIM13,
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GATE_TIM14,
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GATE_TIM15,
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GATE_TIM16,
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GATE_TIM17,
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GATE_DMA1,
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GATE_DMA2,
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GATE_DMAMUX1,
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GATE_DMA3,
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GATE_DMAMUX2,
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GATE_ADC1,
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GATE_ADC2,
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GATE_USBO,
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GATE_TSC,
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GATE_GPIOA,
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GATE_GPIOB,
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GATE_GPIOC,
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GATE_GPIOD,
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GATE_GPIOE,
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GATE_GPIOF,
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GATE_GPIOG,
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GATE_GPIOH,
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GATE_GPIOI,
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GATE_PKA,
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GATE_SAES,
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GATE_CRYP1,
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GATE_HASH1,
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GATE_RNG1,
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GATE_BKPSRAM,
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GATE_AXIMC,
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GATE_MCE,
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GATE_ETH1CK,
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GATE_ETH1TX,
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GATE_ETH1RX,
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GATE_ETH1MAC,
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GATE_FMC,
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GATE_QSPI,
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GATE_SDMMC1,
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GATE_SDMMC2,
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GATE_CRC1,
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GATE_USBH,
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GATE_ETH2CK,
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GATE_ETH2TX,
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GATE_ETH2RX,
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GATE_ETH2MAC,
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GATE_ETH1STP,
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GATE_ETH2STP,
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GATE_MDMA,
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GATE_NB
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};
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#define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\
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[(_id)] = {\
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.offset = (_offset),\
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.bit_idx = (_bit_idx),\
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.set_clr = (_offset_clr),\
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}
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#define CFG_GATE(_id, _offset, _bit_idx)\
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_CFG_GATE(_id, _offset, _bit_idx, 0)
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#define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\
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_CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
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static struct stm32_gate_cfg stm32mp13_gates[] = {
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CFG_GATE(GATE_MCO1, RCC_MCO1CFGR, 12),
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CFG_GATE(GATE_MCO2, RCC_MCO2CFGR, 12),
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CFG_GATE(GATE_DBGCK, RCC_DBGCFGR, 8),
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CFG_GATE(GATE_TRACECK, RCC_DBGCFGR, 9),
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CFG_GATE(GATE_DDRC1, RCC_DDRITFCR, 0),
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CFG_GATE(GATE_DDRC1LP, RCC_DDRITFCR, 1),
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CFG_GATE(GATE_DDRPHYC, RCC_DDRITFCR, 4),
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CFG_GATE(GATE_DDRPHYCLP, RCC_DDRITFCR, 5),
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CFG_GATE(GATE_DDRCAPB, RCC_DDRITFCR, 6),
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CFG_GATE(GATE_DDRCAPBLP, RCC_DDRITFCR, 7),
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CFG_GATE(GATE_AXIDCG, RCC_DDRITFCR, 8),
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CFG_GATE(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9),
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CFG_GATE(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10),
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CFG_GATE_SETCLR(GATE_TIM2, RCC_MP_APB1ENSETR, 0),
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CFG_GATE_SETCLR(GATE_TIM3, RCC_MP_APB1ENSETR, 1),
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CFG_GATE_SETCLR(GATE_TIM4, RCC_MP_APB1ENSETR, 2),
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CFG_GATE_SETCLR(GATE_TIM5, RCC_MP_APB1ENSETR, 3),
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CFG_GATE_SETCLR(GATE_TIM6, RCC_MP_APB1ENSETR, 4),
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CFG_GATE_SETCLR(GATE_TIM7, RCC_MP_APB1ENSETR, 5),
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CFG_GATE_SETCLR(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9),
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CFG_GATE_SETCLR(GATE_SPI2, RCC_MP_APB1ENSETR, 11),
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CFG_GATE_SETCLR(GATE_SPI3, RCC_MP_APB1ENSETR, 12),
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CFG_GATE_SETCLR(GATE_USART3, RCC_MP_APB1ENSETR, 15),
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CFG_GATE_SETCLR(GATE_UART4, RCC_MP_APB1ENSETR, 16),
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CFG_GATE_SETCLR(GATE_UART5, RCC_MP_APB1ENSETR, 17),
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CFG_GATE_SETCLR(GATE_UART7, RCC_MP_APB1ENSETR, 18),
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CFG_GATE_SETCLR(GATE_UART8, RCC_MP_APB1ENSETR, 19),
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CFG_GATE_SETCLR(GATE_I2C1, RCC_MP_APB1ENSETR, 21),
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CFG_GATE_SETCLR(GATE_I2C2, RCC_MP_APB1ENSETR, 22),
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CFG_GATE_SETCLR(GATE_SPDIF, RCC_MP_APB1ENSETR, 26),
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CFG_GATE_SETCLR(GATE_TIM1, RCC_MP_APB2ENSETR, 0),
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CFG_GATE_SETCLR(GATE_TIM8, RCC_MP_APB2ENSETR, 1),
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CFG_GATE_SETCLR(GATE_SPI1, RCC_MP_APB2ENSETR, 8),
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CFG_GATE_SETCLR(GATE_USART6, RCC_MP_APB2ENSETR, 13),
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CFG_GATE_SETCLR(GATE_SAI1, RCC_MP_APB2ENSETR, 16),
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CFG_GATE_SETCLR(GATE_SAI2, RCC_MP_APB2ENSETR, 17),
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CFG_GATE_SETCLR(GATE_DFSDM, RCC_MP_APB2ENSETR, 20),
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CFG_GATE_SETCLR(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21),
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CFG_GATE_SETCLR(GATE_FDCAN, RCC_MP_APB2ENSETR, 24),
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CFG_GATE_SETCLR(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0),
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CFG_GATE_SETCLR(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1),
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CFG_GATE_SETCLR(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2),
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CFG_GATE_SETCLR(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3),
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CFG_GATE_SETCLR(GATE_VREF, RCC_MP_APB3ENSETR, 13),
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CFG_GATE_SETCLR(GATE_DTS, RCC_MP_APB3ENSETR, 16),
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CFG_GATE_SETCLR(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17),
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CFG_GATE_SETCLR(GATE_HDP, RCC_MP_APB3ENSETR, 20),
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CFG_GATE_SETCLR(GATE_SYSCFG, RCC_MP_NS_APB3ENSETR, 0),
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CFG_GATE_SETCLR(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1),
|
||||
CFG_GATE_SETCLR(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8),
|
||||
CFG_GATE_SETCLR(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15),
|
||||
CFG_GATE_SETCLR(GATE_USBPHY, RCC_MP_APB4ENSETR, 16),
|
||||
CFG_GATE_SETCLR(GATE_STGENRO, RCC_MP_APB4ENSETR, 20),
|
||||
CFG_GATE_SETCLR(GATE_LTDC, RCC_MP_NS_APB4ENSETR, 0),
|
||||
CFG_GATE_SETCLR(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8),
|
||||
CFG_GATE_SETCLR(GATE_TZC, RCC_MP_APB5ENSETR, 11),
|
||||
CFG_GATE_SETCLR(GATE_ETZPC, RCC_MP_APB5ENSETR, 13),
|
||||
CFG_GATE_SETCLR(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15),
|
||||
CFG_GATE_SETCLR(GATE_BSEC, RCC_MP_APB5ENSETR, 16),
|
||||
CFG_GATE_SETCLR(GATE_STGENC, RCC_MP_APB5ENSETR, 20),
|
||||
CFG_GATE_SETCLR(GATE_USART1, RCC_MP_APB6ENSETR, 0),
|
||||
CFG_GATE_SETCLR(GATE_USART2, RCC_MP_APB6ENSETR, 1),
|
||||
CFG_GATE_SETCLR(GATE_SPI4, RCC_MP_APB6ENSETR, 2),
|
||||
CFG_GATE_SETCLR(GATE_SPI5, RCC_MP_APB6ENSETR, 3),
|
||||
CFG_GATE_SETCLR(GATE_I2C3, RCC_MP_APB6ENSETR, 4),
|
||||
CFG_GATE_SETCLR(GATE_I2C4, RCC_MP_APB6ENSETR, 5),
|
||||
CFG_GATE_SETCLR(GATE_I2C5, RCC_MP_APB6ENSETR, 6),
|
||||
CFG_GATE_SETCLR(GATE_TIM12, RCC_MP_APB6ENSETR, 7),
|
||||
CFG_GATE_SETCLR(GATE_TIM13, RCC_MP_APB6ENSETR, 8),
|
||||
CFG_GATE_SETCLR(GATE_TIM14, RCC_MP_APB6ENSETR, 9),
|
||||
CFG_GATE_SETCLR(GATE_TIM15, RCC_MP_APB6ENSETR, 10),
|
||||
CFG_GATE_SETCLR(GATE_TIM16, RCC_MP_APB6ENSETR, 11),
|
||||
CFG_GATE_SETCLR(GATE_TIM17, RCC_MP_APB6ENSETR, 12),
|
||||
CFG_GATE_SETCLR(GATE_DMA1, RCC_MP_AHB2ENSETR, 0),
|
||||
CFG_GATE_SETCLR(GATE_DMA2, RCC_MP_AHB2ENSETR, 1),
|
||||
CFG_GATE_SETCLR(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2),
|
||||
CFG_GATE_SETCLR(GATE_DMA3, RCC_MP_AHB2ENSETR, 3),
|
||||
CFG_GATE_SETCLR(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4),
|
||||
CFG_GATE_SETCLR(GATE_ADC1, RCC_MP_AHB2ENSETR, 5),
|
||||
CFG_GATE_SETCLR(GATE_ADC2, RCC_MP_AHB2ENSETR, 6),
|
||||
CFG_GATE_SETCLR(GATE_USBO, RCC_MP_AHB2ENSETR, 8),
|
||||
CFG_GATE_SETCLR(GATE_TSC, RCC_MP_AHB4ENSETR, 15),
|
||||
CFG_GATE_SETCLR(GATE_GPIOA, RCC_MP_NS_AHB4ENSETR, 0),
|
||||
CFG_GATE_SETCLR(GATE_GPIOB, RCC_MP_NS_AHB4ENSETR, 1),
|
||||
CFG_GATE_SETCLR(GATE_GPIOC, RCC_MP_NS_AHB4ENSETR, 2),
|
||||
CFG_GATE_SETCLR(GATE_GPIOD, RCC_MP_NS_AHB4ENSETR, 3),
|
||||
CFG_GATE_SETCLR(GATE_GPIOE, RCC_MP_NS_AHB4ENSETR, 4),
|
||||
CFG_GATE_SETCLR(GATE_GPIOF, RCC_MP_NS_AHB4ENSETR, 5),
|
||||
CFG_GATE_SETCLR(GATE_GPIOG, RCC_MP_NS_AHB4ENSETR, 6),
|
||||
CFG_GATE_SETCLR(GATE_GPIOH, RCC_MP_NS_AHB4ENSETR, 7),
|
||||
CFG_GATE_SETCLR(GATE_GPIOI, RCC_MP_NS_AHB4ENSETR, 8),
|
||||
CFG_GATE_SETCLR(GATE_PKA, RCC_MP_AHB5ENSETR, 2),
|
||||
CFG_GATE_SETCLR(GATE_SAES, RCC_MP_AHB5ENSETR, 3),
|
||||
CFG_GATE_SETCLR(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4),
|
||||
CFG_GATE_SETCLR(GATE_HASH1, RCC_MP_AHB5ENSETR, 5),
|
||||
CFG_GATE_SETCLR(GATE_RNG1, RCC_MP_AHB5ENSETR, 6),
|
||||
CFG_GATE_SETCLR(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8),
|
||||
CFG_GATE_SETCLR(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16),
|
||||
CFG_GATE_SETCLR(GATE_MCE, RCC_MP_AHB6ENSETR, 1),
|
||||
CFG_GATE_SETCLR(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7),
|
||||
CFG_GATE_SETCLR(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8),
|
||||
CFG_GATE_SETCLR(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9),
|
||||
CFG_GATE_SETCLR(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10),
|
||||
CFG_GATE_SETCLR(GATE_FMC, RCC_MP_AHB6ENSETR, 12),
|
||||
CFG_GATE_SETCLR(GATE_QSPI, RCC_MP_AHB6ENSETR, 14),
|
||||
CFG_GATE_SETCLR(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16),
|
||||
CFG_GATE_SETCLR(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17),
|
||||
CFG_GATE_SETCLR(GATE_CRC1, RCC_MP_AHB6ENSETR, 20),
|
||||
CFG_GATE_SETCLR(GATE_USBH, RCC_MP_AHB6ENSETR, 24),
|
||||
CFG_GATE_SETCLR(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27),
|
||||
CFG_GATE_SETCLR(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28),
|
||||
CFG_GATE_SETCLR(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29),
|
||||
CFG_GATE_SETCLR(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30),
|
||||
CFG_GATE_SETCLR(GATE_ETH1STP, RCC_MP_AHB6LPENSETR, 11),
|
||||
CFG_GATE_SETCLR(GATE_ETH2STP, RCC_MP_AHB6LPENSETR, 31),
|
||||
CFG_GATE_SETCLR(GATE_MDMA, RCC_MP_NS_AHB6ENSETR, 0),
|
||||
};
|
||||
|
||||
/* STM32 Divivers definition */
|
||||
enum enum_div_cfg {
|
||||
DIV_RTC,
|
||||
DIV_HSI,
|
||||
DIV_MCO1,
|
||||
DIV_MCO2,
|
||||
DIV_TRACE,
|
||||
DIV_ETH1PTP,
|
||||
DIV_ETH2PTP,
|
||||
DIV_NB
|
||||
};
|
||||
|
||||
static const struct clk_div_table ck_trace_div_table[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
|
||||
{ 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
#define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\
|
||||
[(_id)] = {\
|
||||
.offset = (_offset),\
|
||||
.shift = (_shift),\
|
||||
.width = (_width),\
|
||||
.flags = (_flags),\
|
||||
.table = (_table),\
|
||||
.ready = (_ready),\
|
||||
}
|
||||
|
||||
static const struct stm32_div_cfg stm32mp13_dividers[DIV_NB] = {
|
||||
CFG_DIV(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY),
|
||||
CFG_DIV(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_RDY),
|
||||
CFG_DIV(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_RDY),
|
||||
CFG_DIV(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table, DIV_NO_RDY),
|
||||
CFG_DIV(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_RDY),
|
||||
CFG_DIV(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_RDY),
|
||||
};
|
||||
|
||||
/* STM32 Muxes definition */
|
||||
enum enum_mux_cfg {
|
||||
MUX_ADC1,
|
||||
MUX_ADC2,
|
||||
MUX_DCMIPP,
|
||||
MUX_ETH1,
|
||||
MUX_ETH2,
|
||||
MUX_FDCAN,
|
||||
MUX_FMC,
|
||||
MUX_I2C12,
|
||||
MUX_I2C3,
|
||||
MUX_I2C4,
|
||||
MUX_I2C5,
|
||||
MUX_LPTIM1,
|
||||
MUX_LPTIM2,
|
||||
MUX_LPTIM3,
|
||||
MUX_LPTIM45,
|
||||
MUX_MCO1,
|
||||
MUX_MCO2,
|
||||
MUX_QSPI,
|
||||
MUX_RNG1,
|
||||
MUX_SAES,
|
||||
MUX_SAI1,
|
||||
MUX_SAI2,
|
||||
MUX_SDMMC1,
|
||||
MUX_SDMMC2,
|
||||
MUX_SPDIF,
|
||||
MUX_SPI1,
|
||||
MUX_SPI23,
|
||||
MUX_SPI4,
|
||||
MUX_SPI5,
|
||||
MUX_STGEN,
|
||||
MUX_UART1,
|
||||
MUX_UART2,
|
||||
MUX_UART4,
|
||||
MUX_UART6,
|
||||
MUX_UART35,
|
||||
MUX_UART78,
|
||||
MUX_USBO,
|
||||
MUX_USBPHY,
|
||||
MUX_NB
|
||||
};
|
||||
|
||||
#define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\
|
||||
[_id] = {\
|
||||
.offset = (_offset),\
|
||||
.shift = (_shift),\
|
||||
.width = (_witdh),\
|
||||
.ready = (_ready),\
|
||||
.flags = (_flags),\
|
||||
}
|
||||
|
||||
#define CFG_MUX(_id, _offset, _shift, _witdh)\
|
||||
_CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, 0)
|
||||
|
||||
static const struct stm32_mux_cfg stm32mp13_muxes[] = {
|
||||
CFG_MUX(MUX_I2C12, RCC_I2C12CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_SPI23, RCC_SPI2S23CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_UART35, RCC_UART35CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_UART78, RCC_UART78CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_ADC1, RCC_ADC12CKSELR, 0, 2),
|
||||
CFG_MUX(MUX_ADC2, RCC_ADC12CKSELR, 2, 2),
|
||||
CFG_MUX(MUX_DCMIPP, RCC_DCMIPPCKSELR, 0, 2),
|
||||
CFG_MUX(MUX_ETH1, RCC_ETH12CKSELR, 0, 2),
|
||||
CFG_MUX(MUX_ETH2, RCC_ETH12CKSELR, 8, 2),
|
||||
CFG_MUX(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2),
|
||||
CFG_MUX(MUX_I2C3, RCC_I2C345CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_I2C4, RCC_I2C345CKSELR, 3, 3),
|
||||
CFG_MUX(MUX_I2C5, RCC_I2C345CKSELR, 6, 3),
|
||||
CFG_MUX(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_LPTIM2, RCC_LPTIM23CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_LPTIM3, RCC_LPTIM23CKSELR, 3, 3),
|
||||
CFG_MUX(MUX_MCO1, RCC_MCO1CFGR, 0, 3),
|
||||
CFG_MUX(MUX_MCO2, RCC_MCO2CFGR, 0, 3),
|
||||
CFG_MUX(MUX_RNG1, RCC_RNG1CKSELR, 0, 2),
|
||||
CFG_MUX(MUX_SAES, RCC_SAESCKSELR, 0, 2),
|
||||
CFG_MUX(MUX_SAI1, RCC_SAI1CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_SAI2, RCC_SAI2CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2),
|
||||
CFG_MUX(MUX_SPI1, RCC_SPI2S1CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_SPI4, RCC_SPI45CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_SPI5, RCC_SPI45CKSELR, 3, 3),
|
||||
CFG_MUX(MUX_STGEN, RCC_STGENCKSELR, 0, 2),
|
||||
CFG_MUX(MUX_UART1, RCC_UART12CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_UART2, RCC_UART12CKSELR, 3, 3),
|
||||
CFG_MUX(MUX_UART4, RCC_UART4CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_UART6, RCC_UART6CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_USBO, RCC_USBCKSELR, 4, 1),
|
||||
CFG_MUX(MUX_USBPHY, RCC_USBCKSELR, 0, 2),
|
||||
CFG_MUX(MUX_FMC, RCC_FMCCKSELR, 0, 2),
|
||||
CFG_MUX(MUX_QSPI, RCC_QSPICKSELR, 0, 2),
|
||||
CFG_MUX(MUX_SDMMC1, RCC_SDMMC12CKSELR, 0, 3),
|
||||
CFG_MUX(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3),
|
||||
};
|
||||
|
||||
static const struct clock_config stm32mp13_clock_cfg[] = {
|
||||
};
|
||||
|
||||
static u16 stm32mp13_cpt_gate[GATE_NB];
|
||||
|
||||
static struct clk_stm32_clock_data stm32mp13_clock_data = {
|
||||
.gate_cpt = stm32mp13_cpt_gate,
|
||||
.gates = stm32mp13_gates,
|
||||
.muxes = stm32mp13_muxes,
|
||||
.dividers = stm32mp13_dividers,
|
||||
};
|
||||
|
||||
static const struct stm32_rcc_match_data stm32mp13_data = {
|
||||
.tab_clocks = stm32mp13_clock_cfg,
|
||||
.num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg),
|
||||
.clock_data = &stm32mp13_clock_data,
|
||||
.maxbinding = STM32MP1_LAST_CLK,
|
||||
.clear_offset = RCC_CLR_OFFSET,
|
||||
};
|
||||
|
||||
static const struct of_device_id stm32mp13_match_data[] = {
|
||||
{
|
||||
.compatible = "st,stm32mp13-rcc",
|
||||
.data = &stm32mp13_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32mp13_match_data);
|
||||
|
||||
static int stm32mp1_rcc_init(struct device *dev)
|
||||
{
|
||||
void __iomem *rcc_base;
|
||||
int ret = -ENOMEM;
|
||||
|
||||
rcc_base = of_iomap(dev_of_node(dev), 0);
|
||||
if (!rcc_base) {
|
||||
dev_err(dev, "%pOFn: unable to map resource", dev_of_node(dev));
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = stm32_rcc_init(dev, stm32mp13_match_data, rcc_base);
|
||||
out:
|
||||
if (ret) {
|
||||
if (rcc_base)
|
||||
iounmap(rcc_base);
|
||||
|
||||
of_node_put(dev_of_node(dev));
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int get_clock_deps(struct device *dev)
|
||||
{
|
||||
static const char * const clock_deps_name[] = {
|
||||
"hsi", "hse", "csi", "lsi", "lse",
|
||||
};
|
||||
size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
|
||||
struct clk **clk_deps;
|
||||
int i;
|
||||
|
||||
clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
|
||||
if (!clk_deps)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
|
||||
struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
|
||||
clock_deps_name[i]);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
|
||||
return PTR_ERR(clk);
|
||||
} else {
|
||||
/* Device gets a reference count on the clock */
|
||||
clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
|
||||
clk_put(clk);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret = get_clock_deps(dev);
|
||||
|
||||
if (!ret)
|
||||
ret = stm32mp1_rcc_init(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *child, *np = dev_of_node(dev);
|
||||
|
||||
for_each_available_child_of_node(np, child)
|
||||
of_clk_del_provider(child);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver stm32mp13_rcc_clocks_driver = {
|
||||
.driver = {
|
||||
.name = "stm32mp13_rcc",
|
||||
.of_match_table = stm32mp13_match_data,
|
||||
},
|
||||
.probe = stm32mp1_rcc_clocks_probe,
|
||||
.remove = stm32mp1_rcc_clocks_remove,
|
||||
};
|
||||
|
||||
static int __init stm32mp13_clocks_init(void)
|
||||
{
|
||||
return platform_driver_register(&stm32mp13_rcc_clocks_driver);
|
||||
}
|
||||
core_initcall(stm32mp13_clocks_init);
|
||||
122
drivers/clk/stm32/reset-stm32.c
Normal file
122
drivers/clk/stm32/reset-stm32.c
Normal file
@ -0,0 +1,122 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "clk-stm32-core.h"
|
||||
|
||||
#define STM32_RESET_ID_MASK GENMASK(15, 0)
|
||||
|
||||
struct stm32_reset_data {
|
||||
/* reset lock */
|
||||
spinlock_t lock;
|
||||
struct reset_controller_dev rcdev;
|
||||
void __iomem *membase;
|
||||
u32 clear_offset;
|
||||
};
|
||||
|
||||
static inline struct stm32_reset_data *
|
||||
to_stm32_reset_data(struct reset_controller_dev *rcdev)
|
||||
{
|
||||
return container_of(rcdev, struct stm32_reset_data, rcdev);
|
||||
}
|
||||
|
||||
static int stm32_reset_update(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
|
||||
if (data->clear_offset) {
|
||||
void __iomem *addr;
|
||||
|
||||
addr = data->membase + (bank * reg_width);
|
||||
if (!assert)
|
||||
addr += data->clear_offset;
|
||||
|
||||
writel(BIT(offset), addr);
|
||||
|
||||
} else {
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
|
||||
if (assert)
|
||||
reg |= BIT(offset);
|
||||
else
|
||||
reg &= ~BIT(offset);
|
||||
|
||||
writel(reg, data->membase + (bank * reg_width));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return stm32_reset_update(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return stm32_reset_update(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int stm32_reset_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
u32 reg;
|
||||
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
|
||||
return !!(reg & BIT(offset));
|
||||
}
|
||||
|
||||
static const struct reset_control_ops stm32_reset_ops = {
|
||||
.assert = stm32_reset_assert,
|
||||
.deassert = stm32_reset_deassert,
|
||||
.status = stm32_reset_status,
|
||||
};
|
||||
|
||||
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
|
||||
void __iomem *base)
|
||||
{
|
||||
const struct stm32_rcc_match_data *data = match->data;
|
||||
struct stm32_reset_data *reset_data = NULL;
|
||||
|
||||
data = match->data;
|
||||
|
||||
reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
|
||||
if (!reset_data)
|
||||
return -ENOMEM;
|
||||
|
||||
reset_data->membase = base;
|
||||
reset_data->rcdev.owner = THIS_MODULE;
|
||||
reset_data->rcdev.ops = &stm32_reset_ops;
|
||||
reset_data->rcdev.of_node = dev_of_node(dev);
|
||||
reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
|
||||
reset_data->clear_offset = data->clear_offset;
|
||||
|
||||
return reset_controller_register(&reset_data->rcdev);
|
||||
}
|
||||
8
drivers/clk/stm32/reset-stm32.h
Normal file
8
drivers/clk/stm32/reset-stm32.h
Normal file
@ -0,0 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
|
||||
void __iomem *base);
|
||||
1748
drivers/clk/stm32/stm32mp13_rcc.h
Normal file
1748
drivers/clk/stm32/stm32mp13_rcc.h
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user