arm64: dts: ZynqMP DT changes for v5.12
- Wire clock chips present on boards - Enable reset, qspi, nand, watchdog and DP IPs - Enable phy driver for sata and DP - Add iommu description - Add support for zcu104 revC+ boards - Various small changes - Add missing labels - Fix typos in documentation - Add missing boards -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYBqk0gAKCRDKSWXLKUoM ITbRAKCO+l2ziOzd6ACzNEGAxFtdSPLp3ACfShjLzq0OiHdRFrYhen77PRPJ51Q= =nICr -----END PGP SIGNATURE----- Merge tag 'zynqmp-dt-for-v5.12' of https://github.com/Xilinx/linux-xlnx into arm/dt arm64: dts: ZynqMP DT changes for v5.12 - Wire clock chips present on boards - Enable reset, qspi, nand, watchdog and DP IPs - Enable phy driver for sata and DP - Add iommu description - Add support for zcu104 revC+ boards - Various small changes - Add missing labels - Fix typos in documentation - Add missing boards * tag 'zynqmp-dt-for-v5.12' of https://github.com/Xilinx/linux-xlnx: arm64: dts: zynqmp: Wire up the DisplayPort subsystem arm64: dts: zynqmp: Add DisplayPort subsystem arm64: dts: zynqmp: Add DPDMA node dt-bindings: arm: Fix typo in zcu111 board arm64: dts: zynqmp: Add description for zcu104 revC arm64: dts: zynqmp: Add missing iommu IDs arm64: dts: zynqmp: Add missing lpd watchdog node arm64: dts: zynqmp: Wire zynqmp qspi controller arm64: dts: zynqmp: Wire arasan nand controller arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis arm64: dts: zynqmp: Add label for zynqmp_ipi arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 arm64: dts: zynqmp: Enable reset controller driver arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 arm64: dts: zynqmp: Add address-cells property to interrupt controllers Link: https://lore.kernel.org/r/b1a6f89e-f6b4-757b-daf0-d2f1844b833d@xilinx.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
638f79778d
@ -91,6 +91,7 @@ properties:
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items:
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- enum:
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- xlnx,zynqmp-zcu104-revA
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- xlnx,zynqmp-zcu104-revC
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- xlnx,zynqmp-zcu104-rev1.0
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- const: xlnx,zynqmp-zcu104
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- const: xlnx,zynqmp
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@ -107,7 +108,7 @@ properties:
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items:
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- enum:
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- xlnx,zynqmp-zcu111-revA
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- xlnx,zynqmp-zcu11-rev1.0
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- xlnx,zynqmp-zcu111-rev1.0
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- const: xlnx,zynqmp-zcu111
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- const: xlnx,zynqmp
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@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
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@ -116,6 +116,10 @@
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&nand0 {
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clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&gem0 {
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
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<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
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@ -160,6 +164,10 @@
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clocks = <&zynqmp_clk PCIE_REF>;
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};
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&qspi {
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clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&sata {
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clocks = <&zynqmp_clk SATA_REF>;
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};
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@ -215,3 +223,17 @@
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&watchdog0 {
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clocks = <&zynqmp_clk WDT>;
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};
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&lpd_watchdog {
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clocks = <&zynqmp_clk LPD_WDT>;
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};
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&zynqmp_dpdma {
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clocks = <&zynqmp_clk DPDMA_REF>;
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};
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&zynqmp_dpsub {
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clocks = <&zynqmp_clk TOPSW_LSBUS>,
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<&zynqmp_clk DP_AUDIO_REF>,
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<&zynqmp_clk DP_VIDEO_REF>;
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};
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@ -15,6 +15,7 @@
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP ZCU100 RevC";
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@ -108,6 +109,18 @@
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compatible = "iio-hwmon";
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io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
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};
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si5335a_0: clk26 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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si5335a_1: clk27 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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&dcc {
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@ -224,6 +237,13 @@
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};
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};
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&psgtr {
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status = "okay";
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/* usb3, dps */
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clocks = <&si5335a_0>, <&si5335a_1>;
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clock-names = "ref0", "ref1";
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};
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&rtc {
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status = "okay";
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};
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@ -233,11 +253,13 @@
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status = "okay";
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no-1-8-v;
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disable-wp;
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xlnx,mio-bank = <0>;
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};
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&sdhci1 {
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status = "okay";
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bus-width = <0x4>;
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xlnx,mio-bank = <0>;
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non-removable;
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disable-wp;
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cap-power-off-card;
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@ -293,3 +315,14 @@
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&watchdog0 {
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status = "okay";
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};
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&zynqmp_dpdma {
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status = "okay";
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};
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&zynqmp_dpsub {
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status = "okay";
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phy-names = "dp-phy0", "dp-phy1";
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phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
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<&psgtr 0 PHY_TYPE_DP 1 1>;
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};
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@ -13,6 +13,7 @@
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP ZCU102 RevA";
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@ -132,6 +133,19 @@
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compatible = "iio-hwmon";
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io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
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};
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/* 48MHz reference crystal */
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ref48: ref48M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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refhdmi: refhdmi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <114285000>;
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};
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};
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&can1 {
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@ -483,9 +497,56 @@
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#size-cells = <0>;
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reg = <1>;
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si5341: clock-generator@36 { /* SI5341 - u69 */
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compatible = "silabs,si5341";
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reg = <0x36>;
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};
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&ref48>;
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clock-names = "xtal";
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clock-output-names = "si5341";
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si5341_0: out@0 {
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/* refclk0 for PS-GT, used for DP */
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reg = <0>;
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always-on;
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};
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si5341_2: out@2 {
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/* refclk2 for PS-GT, used for USB3 */
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reg = <2>;
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always-on;
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};
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si5341_3: out@3 {
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/* refclk3 for PS-GT, used for SATA */
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reg = <3>;
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always-on;
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};
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si5341_4: out@4 {
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/* refclk4 for PS-GT, used for PCIE slot */
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reg = <4>;
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always-on;
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};
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si5341_5: out@5 {
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/* refclk5 for PS-GT, used for PCIE */
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reg = <5>;
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always-on;
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};
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si5341_6: out@6 {
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/* refclk6 PL CLK125 */
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reg = <6>;
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always-on;
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};
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si5341_7: out@7 {
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/* refclk7 PL CLK74 */
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reg = <7>;
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always-on;
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};
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si5341_9: out@9 {
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/* refclk9 used for PS_REF_CLK 33.3 MHz */
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reg = <9>;
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always-on;
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};
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};
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};
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i2c@2 {
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#address-cells = <1>;
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@ -526,6 +587,17 @@
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* interrupt-parent = <&>;
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* interrupts = <>;
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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clocks = <&refhdmi>;
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clock-names = "xtal";
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clock-output-names = "si5328";
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si5328_clk: clk0@0 {
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reg = <0>;
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clock-frequency = <27000000>;
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};
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};
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};
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/* 5 - 7 unconnected */
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@ -592,6 +664,13 @@
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status = "okay";
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};
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&psgtr {
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status = "okay";
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/* pcie, sata, usb3, dp */
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clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
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clock-names = "ref0", "ref1", "ref2", "ref3";
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};
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&rtc {
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status = "okay";
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};
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@ -607,12 +686,15 @@
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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phy-names = "sata-phy";
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phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
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};
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/* SD1 with level shifter */
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&sdhci1 {
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status = "okay";
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no-1-8-v;
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xlnx,mio-bank = <1>;
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};
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&uart0 {
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@ -632,3 +714,13 @@
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&watchdog0 {
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status = "okay";
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};
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&zynqmp_dpdma {
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status = "okay";
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};
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&zynqmp_dpsub {
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status = "okay";
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phy-names = "dp-phy0";
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phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
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};
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@ -12,6 +12,7 @@
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP ZCU104 RevA";
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@ -36,6 +37,24 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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clock_8t49n287_5: clk125 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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clock_8t49n287_2: clk26 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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clock_8t49n287_3: clk27 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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&can1 {
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@ -158,6 +177,13 @@
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status = "okay";
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};
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&psgtr {
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status = "okay";
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/* nc, sata, usb3, dp */
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clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
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clock-names = "ref1", "ref2", "ref3";
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};
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&sata {
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status = "okay";
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/* SATA OOB timing settings */
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@ -169,12 +195,15 @@
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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phy-names = "sata-phy";
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phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
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};
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/* SD1 with level shifter */
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&sdhci1 {
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status = "okay";
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no-1-8-v;
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xlnx,mio-bank = <1>;
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disable-wp;
|
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};
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@ -195,3 +224,14 @@
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&watchdog0 {
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status = "okay";
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};
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|
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&zynqmp_dpdma {
|
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status = "okay";
|
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};
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|
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&zynqmp_dpsub {
|
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status = "okay";
|
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phy-names = "dp-phy0", "dp-phy1";
|
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phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
|
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<&psgtr 0 PHY_TYPE_DP 1 3>;
|
||||
};
|
||||
|
||||
293
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
Normal file
293
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
Normal file
@ -0,0 +1,293 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU104
|
||||
*
|
||||
* (C) Copyright 2017 - 2020, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU104 RevC";
|
||||
compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem3;
|
||||
i2c0 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ina226 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
|
||||
};
|
||||
|
||||
clock_8t49n287_5: clk125 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
clock_8t49n287_2: clk26 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
clock_8t49n287_3: clk27 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - IRPS5401_ALERT_B
|
||||
* 1 - HDMI_8T49N241_INT_ALM
|
||||
* 2 - MAX6643_OT_B
|
||||
* 3 - MAX6643_FANFAIL_B
|
||||
* 5 - IIC_MUX_RESET_B
|
||||
* 6 - GEM3_EXP_RESET_B
|
||||
* 7 - FMC_LPC_PRSNT_M2C_B
|
||||
* 4, 10 - 17 - not connected
|
||||
*/
|
||||
};
|
||||
|
||||
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/*
|
||||
* IIC_EEPROM 1kB memory which uses 256B blocks
|
||||
* where every block has different address.
|
||||
* 0 - 256B address 0x54
|
||||
* 256B - 512B address 0x55
|
||||
* 512B - 768B address 0x56
|
||||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom: eeprom@54 { /* u23 */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
|
||||
reg = <0x6c>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x43>; /* pmbus / i2c 0x13 */
|
||||
};
|
||||
irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x44>; /* pmbus / i2c 0x14 */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
u183: ina226@40 { /* u183 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
/* 4, 6 not connected */
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* nc, sata, usb3, dp */
|
||||
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
xlnx,mio-bank = <1>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "okay";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
|
||||
<&psgtr 0 PHY_TYPE_DP 1 3>;
|
||||
};
|
||||
@ -13,6 +13,7 @@
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU106 RevA";
|
||||
@ -132,6 +133,19 @@
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
|
||||
};
|
||||
|
||||
/* 48MHz reference crystal */
|
||||
ref48: ref48M {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
refhdmi: refhdmi {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <114285000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
@ -142,6 +156,17 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "okay";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
|
||||
<&psgtr 0 PHY_TYPE_DP 1 3>;
|
||||
};
|
||||
|
||||
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
@ -482,7 +507,45 @@
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si5341: clock-generator@36 { /* SI5341 - u69 */
|
||||
compatible = "silabs,si5341";
|
||||
reg = <0x36>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&ref48>;
|
||||
clock-names = "xtal";
|
||||
clock-output-names = "si5341";
|
||||
|
||||
si5341_0: out@0 {
|
||||
/* refclk0 for PS-GT, used for DP */
|
||||
reg = <0>;
|
||||
always-on;
|
||||
};
|
||||
si5341_2: out@2 {
|
||||
/* refclk2 for PS-GT, used for USB3 */
|
||||
reg = <2>;
|
||||
always-on;
|
||||
};
|
||||
si5341_3: out@3 {
|
||||
/* refclk3 for PS-GT, used for SATA */
|
||||
reg = <3>;
|
||||
always-on;
|
||||
};
|
||||
si5341_6: out@6 {
|
||||
/* refclk6 PL CLK125 */
|
||||
reg = <6>;
|
||||
always-on;
|
||||
};
|
||||
si5341_7: out@7 {
|
||||
/* refclk7 PL CLK74 */
|
||||
reg = <7>;
|
||||
always-on;
|
||||
};
|
||||
si5341_9: out@9 {
|
||||
/* refclk9 used for PS_REF_CLK 33.3 MHz */
|
||||
reg = <9>;
|
||||
always-on;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
@ -520,6 +583,22 @@
|
||||
reg = <4>;
|
||||
si5328: clock-generator@69 {/* SI5328 - u20 */
|
||||
reg = <0x69>;
|
||||
/*
|
||||
* Chip has interrupt present connected to PL
|
||||
* interrupt-parent = <&>;
|
||||
* interrupts = <>;
|
||||
*/
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&refhdmi>;
|
||||
clock-names = "xtal";
|
||||
clock-output-names = "si5328";
|
||||
|
||||
si5328_clk: clk0@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
i2c@5 {
|
||||
@ -591,6 +670,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* nc, sata, usb3, dp */
|
||||
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@ -606,12 +692,15 @@
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU111 RevA";
|
||||
@ -116,6 +117,13 @@
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
|
||||
};
|
||||
|
||||
/* 48MHz reference crystal */
|
||||
ref48: ref48M {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
@ -374,9 +382,46 @@
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si5341: clock-generator@36 { /* SI5341 - u46 */
|
||||
compatible = "silabs,si5341";
|
||||
reg = <0x36>;
|
||||
};
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&ref48>;
|
||||
clock-names = "xtal";
|
||||
clock-output-names = "si5341";
|
||||
|
||||
si5341_0: out@0 {
|
||||
/* refclk0 for PS-GT, used for DP */
|
||||
reg = <0>;
|
||||
always-on;
|
||||
};
|
||||
si5341_2: out@2 {
|
||||
/* refclk2 for PS-GT, used for USB3 */
|
||||
reg = <2>;
|
||||
always-on;
|
||||
};
|
||||
si5341_3: out@3 {
|
||||
/* refclk3 for PS-GT, used for SATA */
|
||||
reg = <3>;
|
||||
always-on;
|
||||
};
|
||||
si5341_5: out@5 {
|
||||
/* refclk5 PL CLK100 */
|
||||
reg = <5>;
|
||||
always-on;
|
||||
};
|
||||
si5341_6: out@6 {
|
||||
/* refclk6 PL CLK125 */
|
||||
reg = <6>;
|
||||
always-on;
|
||||
};
|
||||
si5341_9: out@9 {
|
||||
/* refclk9 used for PS_REF_CLK 33.3 MHz */
|
||||
reg = <9>;
|
||||
always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
@ -410,7 +455,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si5328: clock-generator@69 { /* SI5328 - u48 */
|
||||
si5382: clock-generator@69 { /* SI5382 - u48 */
|
||||
reg = <0x69>;
|
||||
};
|
||||
};
|
||||
@ -497,6 +542,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* nc, sata, usb3, dp */
|
||||
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@ -512,12 +564,15 @@
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
@ -529,3 +584,14 @@
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "okay";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
|
||||
<&psgtr 0 PHY_TYPE_DP 1 1>;
|
||||
};
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
|
||||
#include <dt-bindings/power/xlnx-zynqmp-power.h>
|
||||
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
|
||||
|
||||
@ -99,7 +100,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
zynqmp_ipi {
|
||||
zynqmp_ipi: zynqmp_ipi {
|
||||
compatible = "xlnx,zynqmp-ipi-mailbox";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 35 4>;
|
||||
@ -187,6 +188,11 @@
|
||||
xlnx_aes: zynqmp-aes {
|
||||
compatible = "xlnx,zynqmp-aes";
|
||||
};
|
||||
|
||||
zynqmp_reset: reset-controller {
|
||||
compatible = "xlnx,zynqmp-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -265,6 +271,8 @@
|
||||
interrupts = <0 124 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14e8>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
@ -276,6 +284,8 @@
|
||||
interrupts = <0 125 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14e9>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
@ -287,6 +297,8 @@
|
||||
interrupts = <0 126 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ea>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
@ -298,6 +310,8 @@
|
||||
interrupts = <0 127 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14eb>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
@ -309,6 +323,8 @@
|
||||
interrupts = <0 128 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ec>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
@ -320,6 +336,8 @@
|
||||
interrupts = <0 129 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ed>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
@ -331,6 +349,8 @@
|
||||
interrupts = <0 130 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ee>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
@ -342,11 +362,14 @@
|
||||
interrupts = <0 131 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ef>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f9010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0 0xf9010000 0x0 0x10000>,
|
||||
<0x0 0xf9020000 0x0 0x20000>,
|
||||
@ -369,6 +392,8 @@
|
||||
interrupts = <0 77 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x868>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
@ -380,6 +405,8 @@
|
||||
interrupts = <0 78 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x869>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
@ -391,6 +418,8 @@
|
||||
interrupts = <0 79 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86a>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
@ -402,6 +431,8 @@
|
||||
interrupts = <0 80 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86b>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
@ -413,6 +444,8 @@
|
||||
interrupts = <0 81 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86c>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
@ -424,6 +457,8 @@
|
||||
interrupts = <0 82 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86d>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
@ -435,6 +470,8 @@
|
||||
interrupts = <0 83 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86e>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
@ -446,6 +483,8 @@
|
||||
interrupts = <0 84 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86f>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
@ -456,6 +495,20 @@
|
||||
interrupts = <0 112 4>;
|
||||
};
|
||||
|
||||
nand0: nand-controller@ff100000 {
|
||||
compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xff100000 0x0 0x1000>;
|
||||
clock-names = "controller", "bus";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 14 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x872>;
|
||||
power-domains = <&zynqmp_firmware PD_NAND>;
|
||||
};
|
||||
|
||||
gem0: ethernet@ff0b0000 {
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
@ -465,6 +518,8 @@
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x874>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_0>;
|
||||
};
|
||||
|
||||
@ -477,6 +532,8 @@
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x875>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_1>;
|
||||
};
|
||||
|
||||
@ -489,6 +546,8 @@
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x876>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_2>;
|
||||
};
|
||||
|
||||
@ -501,12 +560,15 @@
|
||||
clock-names = "pclk", "hclk", "tx_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x877>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_3>;
|
||||
};
|
||||
|
||||
gpio: gpio@ff0a0000 {
|
||||
compatible = "xlnx,zynqmp-gpio-1.0";
|
||||
status = "disabled";
|
||||
#address-cells = <0>;
|
||||
#gpio-cells = <0x2>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
@ -576,6 +638,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
qspi: spi@ff0f0000 {
|
||||
compatible = "xlnx,zynqmp-qspi-1.0";
|
||||
status = "disabled";
|
||||
clock-names = "ref_clk", "pclk";
|
||||
interrupts = <0 15 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
num-cs = <1>;
|
||||
reg = <0x0 0xff0f0000 0x0 0x1000>,
|
||||
<0x0 0xc0000000 0x0 0x8000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x873>;
|
||||
power-domains = <&zynqmp_firmware PD_QSPI>;
|
||||
};
|
||||
|
||||
psgtr: phy@fd400000 {
|
||||
compatible = "xlnx,zynqmp-psgtr-v1.1";
|
||||
status = "disabled";
|
||||
@ -602,6 +680,9 @@
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 133 4>;
|
||||
power-domains = <&zynqmp_firmware PD_SATA>;
|
||||
#stream-id-cells = <4>;
|
||||
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
|
||||
<&smmu 0x4c2>, <&smmu 0x4c3>;
|
||||
};
|
||||
|
||||
sdhci0: mmc@ff160000 {
|
||||
@ -611,6 +692,8 @@
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0x0 0xff160000 0x0 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x870>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "clk_out_sd0", "clk_in_sd0";
|
||||
power-domains = <&zynqmp_firmware PD_SD_0>;
|
||||
@ -623,6 +706,8 @@
|
||||
interrupts = <0 49 4>;
|
||||
reg = <0x0 0xff170000 0x0 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x871>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "clk_out_sd1", "clk_in_sd1";
|
||||
power-domains = <&zynqmp_firmware PD_SD_1>;
|
||||
@ -631,6 +716,7 @@
|
||||
smmu: iommu@fd800000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x0 0xfd800000 0x0 0x20000>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
#global-interrupts = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
@ -753,5 +839,45 @@
|
||||
reg = <0x0 0xfd4d0000 0x0 0x1000>;
|
||||
timeout-sec = <10>;
|
||||
};
|
||||
|
||||
lpd_watchdog: watchdog@ff150000 {
|
||||
compatible = "cdns,wdt-r1p2";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 52 1>;
|
||||
reg = <0x0 0xff150000 0x0 0x1000>;
|
||||
timeout-sec = <10>;
|
||||
};
|
||||
|
||||
zynqmp_dpdma: dma-controller@fd4c0000 {
|
||||
compatible = "xlnx,zynqmp-dpdma";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd4c0000 0x0 0x1000>;
|
||||
interrupts = <0 122 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
clock-names = "axi_clk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
zynqmp_dpsub: display@fd4a0000 {
|
||||
compatible = "xlnx,zynqmp-dpsub-1.7";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd4a0000 0x0 0x1000>,
|
||||
<0x0 0xfd4aa000 0x0 0x1000>,
|
||||
<0x0 0xfd4ab000 0x0 0x1000>,
|
||||
<0x0 0xfd4ac000 0x0 0x1000>;
|
||||
reg-names = "dp", "blend", "av_buf", "aud";
|
||||
interrupts = <0 119 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
clock-names = "dp_apb_clk", "dp_aud_clk",
|
||||
"dp_vtc_pixel_clk_in";
|
||||
power-domains = <&zynqmp_firmware PD_DP>;
|
||||
resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
|
||||
dma-names = "vid0", "vid1", "vid2", "gfx0";
|
||||
dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
|
||||
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
|
||||
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
|
||||
<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user