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spi: tegra114: add support for gpio based CS

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This patch adds support for GPIO based CS control through SPI core
function spi_set_cs.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sowjanya Komatineni 2019-05-13 22:03:52 -07:00 committed by Mark Brown
parent 3393f7d924
commit 63c1440596
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GPG Key ID: 24D68B725D5487D0
1 changed files with 13 additions and 0 deletions
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13
drivers/spi/spi-tegra114.c
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@ -776,6 +776,10 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
} else
tegra_spi_writel(tspi, command1, SPI_COMMAND1);
/* GPIO based chip select control */
if (spi->cs_gpiod)
gpiod_set_value(spi->cs_gpiod, 1);
command1 |= SPI_CS_SW_HW;
if (spi->mode & SPI_CS_HIGH)
command1 |= SPI_CS_SW_VAL;
@ -864,6 +868,10 @@ static int tegra_spi_setup(struct spi_device *spi)
}
spin_lock_irqsave(&tspi->lock, flags);
/* GPIO based chip select control */
if (spi->cs_gpiod)
gpiod_set_value(spi->cs_gpiod, 0);
val = tspi->def_command1_reg;
if (spi->mode & SPI_CS_HIGH)
val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
@ -893,6 +901,10 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
/* GPIO based chip select control */
if (spi->cs_gpiod)
gpiod_set_value(spi->cs_gpiod, 0);
if (cs_val)
tspi->command1_reg |= SPI_CS_SW_VAL;
else
@ -1199,6 +1211,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
master->max_speed_hz = 25000000; /* 25MHz */
/* the spi->mode bits understood by this driver: */
master->use_gpio_descriptors = true;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);